Intel CONTROLLERS 413808 - Manual (Page 637)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 637
Timers—Intel ® 413808 and 413812
11.4.3 Timer Count Register – TCR0:1
The Timer Count Register (TCRx) is a 32-bit register that contains the timer’s current
count. The register value decrements with each timer clock tick. When this register
value decrements to zero (terminal count), a timer interrupt is generated. When
TMRx.reload is not set for the timer, the status bit in the timer mode register (TMRx.tc)
is set and remains set until the TMRx register is accessed. Table 422 shows the timer
count register.
The valid programmable range is from 1H to FFFF FFFFH. Avoid programming TCRx to 0
as it has varying results as described in Section 11.5, “Uncommon TCRX and TRRX
Conditions” on page 640 . User software can read or write TCRx whether the timer is
running or stopped. Bit 3 of TMRx determines user read/write control
( Section 11.4.2.5 ). The TCRx value is undefined after hardware or software reset.
11.4.4 Timer Reload Register – TRR0:1
The Timer Reload Register (TRRx; Table 423 ) is a 32-bit register that contains the
timer’s reload count. The timer loads the reload count value into TCRx when
TMRx.reload is set (1), TMRx.enable is set (1) and TCRx equals zero.
As with TCRx, the valid programmable range is from 1H to FFFF FFFFH. Avoid
programming a value of 0, as it may prevent TINTx from asserting continuously. (See
Section 11.5, “Uncommon TCRX and TRRX Conditions” on page 640 for more
information.)
User software can access TRRx whether the timer is running or stopped. Bit 3 of TMRx
determines read/write control ( Section 11.4.2.5, “Bits 4, 5 — Timer Input Clock Select
(TMRx.csel1:0)” on page 636 ). TRRx value is undefined after hardware or software
reset.
Table 422. Timer Count Register – TCRx
31:00 0000 0000H Timer Count Value — TCRx.d31:0
MMR
CP
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor
Coprocessor address
TCR0: CP6, Page 9, Register 2
TCR1: CP6, Page 9, Register 3
Table 423. Timer Reload Register – TRRx
31:00 0000 0000H Timer Auto-Reload Value — TRRx.d31:0
MMR
CP
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor
Coprocessor address
TRR0: CP6, Page 9, Register 4
TRR1: CP6, Page 9, Register 5