Intel CONTROLLERS 413808 - Manual (Page 253)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 253
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.3.5 Outbound Configuration Cycle Translation
The outbound ATU provides a port programming model for outbound configuration
cycles.
Performing an outbound configuration cycle to the PCI Express Link involves up to two
internal bus cycles:
1. Writing Outbound Configuration Cycle Address Register (OCCAR) with the bus,
device, function, and register number used during the configuration cycle. The
value of this register directly maps to bytes 8-11 of the configuration transaction
header. See Section 3.17.44, “PCI Express Message Control/Status Register -
PEMCSR” on page 333 for information regarding configuration address cycle
formats. This IB bus cycle enables the transaction.
2. Writing or reading the Outbound Configuration Cycle Data Register (OCCDR). A
read causes a configuration cycle read to the PCI Express Link with the address in
the outbound configuration cycle address register. Note that the Internal Bus read
is executed as a split transaction. Similarly, a write initiates a configuration cycle
write to PCI with the write data from the second processor cycle. Configuration
cycles are non-burst and restricted to a single 32-bit word cycle
11
. This IB bus cycle
executes the transaction.
When the Configuration Cycle Data Register is written, the data is latched and
forwarded to the PCI Express Link. The Configuration Request TLP always uses
function 0.
Note: Outbound configuration cycle data registers are not physical registers. They are a
4138xx memory mapped addresses used to initiate a transaction with the address in
the associated address register. When the data register is accessed, the address is
pulled from the “Outbound Configuration Cycle Address Register - OCCAR” to generate
the TLP header and any write data is placed directly in the ONPDQ.
3.3.5.1 Outbound Configuration Cycle Error Conditions
When issuing configuration requests, the ATU must deal with receiving completions
with Unsupported Request (UR) and Completer Abort (CA) status. When a UR or CA is
received, the ATU interrupts the core by setting the Received Master Abort / Received
Target Abort status in the “ATU Interrupt Status Register - ATUISR” on page 329 . The
read cycle is terminated with a DABORT on the internal bus.
When the completion is returned with poisoned data, the ATU sets the Detected Parity
Error Interrupt status bit in the “ATU Interrupt Status Register - ATUISR” on page 329 .
The data is issued on the internal bus with bad parity.
3.3.5.2 Outbound Configuration Completions with Retry Status (CRS)
When issuing configuration requests, the ATU must deal with receiving a Configuration
Request Retry Status (CRS). When a CRS is received, the ATU interrupts the core by
setting the Received Configuration Retry Status in the “ATU Interrupt Status Register -
ATUISR” on page 329 . A configuration read that is completed with a CRS also results in
a DABORT on the internal bus.
It is the responsibility of the software to reissue the configuration transaction.
11.The user should designate the memory region containing the OCCDR as non-cachable and
non-bufferable from the Intel XScale
®
processor. This insures that all load/stores to the OCCDR
are only of DWORD quantities. In event the user inadvertently issues a read to the OCCDR that
crosses a DWORD address boundary, the ATU target aborts the transaction. All writes are
terminated with a Single-Phase-Disconnect and only bytes 3:0 are relevant.