Intel CONTROLLERS 413808 - Manual (Page 357)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 357
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.72 PCI Express Uncorrectable Error Severity - ERRUNC_SEV
The Uncorrectable Error Severity register controls whether an individual uncorrectable
error is reported as a non-fatal or fatal error. An error is reported as fatal when the
corresponding error bit in the severity register is set. When the bit is cleared, the
corresponding error is considered non-fatal.
Note: All bits in this register are sticky through reset.
Table 212. PCI Express Uncorrectable Error Severity - ERRUNC_SEV
Bit Default Description
31:21 0 Preserved
20 0 Unsupported Request Error Status Severity
19 0 ECRC Check Severity
18 1 Malformed TLP Severity
17 1 Receiver Overflow Severity
16 0 Unexpected Completion Severity
15 0 Completer Abort Severity
14 0 Completion Time Out Severity
13 1 Flow Control Protocol Error Status Severity
12 0 Poisoned TLP Received Severity
11:5 0 Preserved
4 1 Data Link Protocol Error Severity
3:1 0 Preserved
0 1 Training Error Severity
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
pr
pr
pr
pr
pr
pr
rw
rw
S S S S S S S S S S S
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+10CH