Intel CONTROLLERS 413808 - Manual (Page 614)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
614 Order Number: 317805-001US
10.7.22 FIQ Interrupt Source Register 1 — FINTSRC1
The FIQ Interrupt Source register 1 is a 32-bit Coprocessor 6 control register used to
specify which interrupts that are steered to the internal FIQ exception are unmasked by
the INTCTL1 register and active. The INTSTR1 control register is used to steer
individual interrupts to the FIQ exception.
The FINTSRC1 register may be used by an Interrupt Service Routine (ISR) to
determine quickly the source of an FIQ interrupt.
Table 404. FIQ Interrupt Source Register 1 — FINTSRC1 (Sheet 1 of 2)
Bit Default Description
31 0
2
Reserved.
30 0
2
Messaging Unit Error Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
29:28 0
2
Reserved.
27 0
2
Reserved.
26 0
2
Reserved.
25 0
2
Reserved.
24 0
2
Reserved.
23 0
2
ATU Error Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
22 0
2
ATU Configuration Register Write Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
21 0
2
Peripheral Bus Interface Unit Error Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
20 0
2
UART 1 Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
19 0
2
UART 0 Interrupt
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
18:08 0000H Reserved.
7 0
2
XINT15# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
6 0
2
XINT14# Interrupt Mask
0 = Not Interrupting or Not steered to internal FIQ exception or masked by INTCTL1
1 = Interrupting and steered to internal FIQ exception and unmasked by INTCTL1
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 7, Register 1