Intel CONTROLLERS 413808 - Manual (Page 170)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
170 Order Number: 317805-001US
2.14.29 Inbound ATU Translate Value Register 0 - IATVR0
The Inbound ATU Translate Value Register 0 (IATVR0) in conjunction with the “Inbound
ATU Upper Translate Value Register 0 - IAUTVR0” on page 170 contain bits 35 to 12 of
the internal bus address used to convert PCI bus addresses. The converted address is
driven on the internal bus as a result of the inbound ATU address translation.
2.14.30 Inbound ATU Upper Translate Value Register 0 - IAUTVR0
The Inbound ATU Upper Translate Value Register 0 (IAUTVR0) in conjunction with the
“Inbound ATU Translate Value Register 0 - IATVR0” on page 170 contain bits 35 to12 of
the internal bus address used to convert PCI bus addresses. The converted address is
driven on the internal bus as a result of the inbound ATU address translation.
Table 56. Inbound ATU Translate Value Register 0 - IATVR0
Bit Default Description
31:12 FF000H
Inbound ATU Translation Value 0 - This value represents bits 31 to 12 of the internal bus address used
to convert the PCI address to internal bus addresses. This value must be naturally aligned with the
IABAR0 register’s programmed value (see Section 2.14.23, “Determining Block Sizes for Base Address
Registers” on page 164 ).The default address allows the ATU to access the internal 4138xx
memory-mapped registers.
11:01 000H Reserved
00 0
Big Endian Byte Swap enable - When set the ATU performs a byte swap on all PCI read/write
transactions through BAR0. When clear, no swap is performed. Refer to Section 2.3, “Big Endian Byte
Swapping” on page 78 for more details.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+044H
Table 57. Inbound ATU Upper Translate Value Register 0 - IAUTVR0
Bit Default Description
31:04 000 0000H Reserved
3:0 0H
Inbound Upper ATU Translation Value 0 - This value represents bits 35 to 32 of the internal bus address
used to convert the PCI address to internal bus addresses. The default address allows the ATU to access
the internal 4138xx memory-mapped registers.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+048H