Document Outline

• Intel® 413808 and 413812 I/O Controllers in TPER Mode
• 1.0 Introduction
  • Table 1. Intel® 413808 and 413812 I/O Controllers in TPER Mode/Firmware Mapping
  • Figure 1. TPER Architecture Overview
  • 1.1 Design-in Considerations
    • 1.1.1 Software
  • 1.2 Documentation References
    • Table 2. Documentation References
  • 1.3 About This Document
    • 1.3.1 How To Read This Document
    • 1.3.2 Other Relevant Documents
  • 1.4 About the Intel® 413808 and 413812 I/O Controllers in TPER Mode
    • Figure 2. Intel® 413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram
  • 1.5 Intel® 413808 and 413812 I/O Controllers in TPER Mode Features
    • 1.5.1 Host Interface
    • 1.5.2 Intel XScale® Processor
    • 1.5.3 Internal Busses
    • 1.5.4 Application DMA Controller
    • 1.5.5 Address Translation Unit
    • 1.5.6 Messaging Unit
    • 1.5.7 DDR Memory Controller
    • 1.5.8 Peripheral Bus Interface
    • 1.5.9 Performance Monitoring Unit
    • 1.5.10 I2C Bus Interface Unit
    • 1.5.11 UART Unit
    • 1.5.12 Interrupt Controller Unit
    • 1.5.13 Internal Bus System Controller
    • 1.5.14 Inter-Processor Communication
    • 1.5.15 Inter-Processor Messaging Unit
    • 1.5.16 Timers
    • 1.5.17 GPIO
    • 1.5.18 FSENG
  • 1.6 Terminology and Conventions
    • 1.6.1 Representing Numbers
    • 1.6.2 Fields
    • 1.6.3 Specifying Bit and Signal Values
    • 1.6.4 Signal Name Conventions
    • 1.6.5 Terminology
• 2.0 Address Translation Unit (PCI-X)
  • 2.1 Overview
    • Figure 3. ATU Block Diagram
    • Figure 4. ATU Queue Architecture Block Diagram
  • 2.2 ATU Address Translation
    • Table 3. ATU Command Support
    • 2.2.1 Inbound Transactions
      • 2.2.1.1 Inbound Address Translation
        • Equation 1. Inbound Address Detection
        • Figure 5. Inbound Address Detection
        • Equation 2. Inbound Translation
        • Figure 6. Inbound Translation Example
      • 2.2.1.2 Inbound Write Transaction
      • 2.2.1.3 Inbound Read Transaction
      • 2.2.1.4 Inbound Configuration Cycle Translation
      • 2.2.1.5 Discard Timers
    • 2.2.2 Outbound Transactions- Single Address Cycle (SAC) Internal Bus Transactions
      • 2.2.2.1 Outbound Address Translation - Internal Bus Transactions
        • Figure 7. 4 Gbyte Section 0 of the Internal Bus Memory Map
        • Table 4. Outbound Address Translation Control
      • 2.2.2.2 Outbound Address Translation Windows
        • Figure 8. Outbound Address Translation Windows
        • Table 5. Internal Bus-to-PCI Command Translation for Memory Windows
        • Table 6. Internal Bus-to-PCI Command Translation for I/O Window
        • Equation 3. Outbound Address Translation
        • Equation 4. I/O Transactions
    • 2.2.3 Outbound Write Transaction
    • 2.2.4 Outbound Read Transaction
    • 2.2.5 Outbound Configuration Cycle Translation
      • 2.2.5.1 PCI-X Mode 1 Considerations for Outbound Configuration Cycles
      • 2.2.5.2 PCI-X Mode 2 Considerations for Outbound Configuration Cycles
      • 2.2.5.3 Outbound Configuration Cycle Error Conditions
    • 2.2.6 Internal Bus Operation
  • 2.3 Big Endian Byte Swapping
    • 2.3.1 Inbound Byte Swapping
      • Figure 9. Inbound Byte Swapping for 32-bit PCI
      • Figure 10. Inbound Byte Swapping for 64-bit PCI
    • 2.3.2 Outbound Byte Swapping
      • Figure 11. Outbound Byte Swapping for Transaction with Byte Count of 1
      • Figure 12. Outbound Byte Swapping for Transaction with Byte Count of 2
      • Figure 13. Outbound Byte Swapping for Transaction with Byte Count of 3 or Larger
  • 2.4 CompactPCI Hot-Swap
    • 2.4.1 Pin Interface
      • Table 7. Compact PCI Hot-Swap
      • 2.4.1.1 Compact PCI Hot-Swap Mode Select
        • Table 8. HS_FREQ Encoding
  • 2.5 Expansion ROM Translation Unit
  • 2.6 ATU Queue Architecture
    • 2.6.1 Inbound Queues
      • Table 9. Inbound Queues
      • 2.6.1.1 Inbound Write Queue Structure
      • 2.6.1.2 Inbound Read Queue Structure
        • Table 10. Inbound Read Prefetch Data Sizes
      • 2.6.1.3 Inbound Delayed Write Queue
      • 2.6.1.4 Inbound Transaction Queues Command Translation Summary
        • Table 11. PCI to Internal Bus Command Translation for All Inbound Transactions
    • 2.6.2 Outbound Queues
      • Table 12. Outbound Queues
      • 2.6.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes
    • 2.6.3 Transaction Ordering
      • Table 13. ATU Inbound Data Flow Ordering Rules
      • Table 14. ATU Outbound Data Flow Ordering Rules
      • 2.6.3.1 Transaction Ordering Summary
        • Table 15. Inbound Transaction Ordering Summary
        • Table 16. Outbound Transaction Ordering Summary
    • 2.6.4 Byte Parity Checking and Generation
      • 2.6.4.1 Parity Generation
        • Equation 5. D_PARITY0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]
        • Table 17. Parity Generation
      • 2.6.4.2 Parity Checking
        • Equation 6. PARITY_RESULT = A_PARITY0 XOR A[0] XOR A[1] XOR A[2] XOR A[3] XOR A[4] XOR A[5] XOR A[6] XOR A[7]
        • Equation 7. PARITY_RESULT = D_PARITY0 XOR D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]
      • 2.6.4.3 Parity Disabled
  • 2.7 ATU Error Conditions
    • 2.7.1 Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface
    • 2.7.2 Correctable Address and Correctable Attribute Errors on the PCI Interface
    • 2.7.3 Uncorrectable Data Errors on the PCI Interface
      • 2.7.3.1 Outbound Read Request Uncorrectable Data Errors
        • 2.7.3.1.1 Immediate Data Transfer
        • 2.7.3.1.2 Split Response Termination
      • 2.7.3.2 Outbound Write Request Uncorrectable Data Errors
        • 2.7.3.2.1 Outbound Writes that are not MSI (Message Signaled Interrupts)
        • 2.7.3.2.2 MSI Outbound Writes
      • 2.7.3.3 Inbound Read Completions Uncorrectable Data Errors
      • 2.7.3.4 Inbound Configuration Write Completion Message Uncorrectable Data Errors
      • 2.7.3.5 Inbound Read Request Uncorrectable Data Errors
        • 2.7.3.5.1 Immediate Data Transfer
        • 2.7.3.5.2 Split Response Termination
      • 2.7.3.6 Inbound Write Request Uncorrectable Data Errors
      • 2.7.3.7 Outbound Read Completion Uncorrectable Data Errors
      • 2.7.3.8 Outbound Split Write Uncorrectable Data Error Message
      • 2.7.3.9 Inbound Configuration Write Request
        • 2.7.3.9.1 Conventional PCI Mode
        • 2.7.3.9.2 PCI-X Mode
      • 2.7.3.10 Split Completion Messages
    • 2.7.4 Correctable Data Errors on the PCI Interface
      • 2.7.4.1 Inbound Read Request Correctable Data Errors
        • 2.7.4.1.1 Immediate Data Transfer
        • 2.7.4.1.2 Split Response Termination
      • 2.7.4.2 Inbound Write Request Correctable Data Errors
      • 2.7.4.3 Outbound Read Completion Correctable Data Errors
      • 2.7.4.4 Inbound Configuration Write Request
      • 2.7.4.5 Split Completion Messages
    • 2.7.5 Master Aborts on the PCI Interface
      • 2.7.5.1 Master Aborts for Outbound Read or Write Request
      • 2.7.5.2 Inbound Read Completion or Inbound Configuration Write Completion Message
      • 2.7.5.3 Master-Aborts Signaled by the ATU as a Target
        • 2.7.5.3.1 Uncorrectable Address Errors
        • 2.7.5.3.2 Internal Bus Master-Abort
    • 2.7.6 Target Aborts on the PCI Interface
      • 2.7.6.1 Target Aborts for Outbound Read Request or Outbound Write Request
      • 2.7.6.2 Inbound Read Completion or Inbound Configuration Write Completion Message
      • 2.7.6.3 Target-Aborts Signaled by the ATU as a Target
        • 2.7.6.3.1 Internal Bus Master Abort
        • 2.7.6.3.2 Internal Bus Target Abort
        • 2.7.6.3.3 Inbound EROM Memory Write
    • 2.7.7 Corrupted or Unexpected Split Completions
      • 2.7.7.1 Completer Address
      • 2.7.7.2 Completer Attributes
    • 2.7.8 SERR# Assertion and Detection
    • 2.7.9 Internal Bus Error Conditions
      • 2.7.9.1 Master Abort on the Internal Bus
        • 2.7.9.1.1 Inbound Write Request
        • 2.7.9.1.2 Inbound Read Request
      • 2.7.9.2 Target Abort on the Internal Bus
        • 2.7.9.2.1 Conventional Mode
        • 2.7.9.2.2 PCI-X Mode
      • 2.7.9.3 Parity Error on the Internal Bus
        • 2.7.9.3.1 Conventional Mode
        • 2.7.9.3.2 PCI-X Mode
    • 2.7.10 ATU Error Summary
      • Table 18. ATU Error Reporting Summary - PCI Interface (Sheet 1 of 5)
      • Table 19. ATU Error Reporting Summary - Internal Bus Interface
  • 2.8 Message-Signaled Interrupts
  • 2.9 Internal Interrupts
  • 2.10 Vital Product Data
    • 2.10.1 Configuring Vital Product Data Operation
    • 2.10.2 Accessing Vital Product Data
      • 2.10.2.1 Reading Vital Product Data
      • 2.10.2.2 Writing Vital Product Data
  • 2.11 Multi-Function Support
    • 2.11.1 PCI-X Interface Control Parameters
      • Table 20. PCI-X Interface Control Parameters Usage
    • 2.11.2 PCI-X Interface Status Reporting
      • Table 21. PCI-X Host Interface Status Reporting Usage
  • 2.12 Central Resource Functionality
    • 2.12.1 Multi-Function Support
    • 2.12.2 Outbound Transactions
    • 2.12.3 PCI Reset (P_RSTOUT#)
    • 2.12.4 PCI Clock Outputs (P_CLKOUT, P_CLKO[3:0])
    • 2.12.5 External Clock Driver (CR_FREQ[1:0])
      • Table 22. CR_FREQ[1:0] Encoding
    • 2.12.6 Bus Mode and Frequency Initialization
      • Table 23. Device Mode/Frequency Capability Reporting
      • Table 24. PCI Bus Frequency Initialization
      • Table 25. PCI-X Initialization Pattern
      • Figure 14. PCI-X Initialization Pattern Setting / Drive
  • 2.13 Embedded Bridge Functionality
  • 2.14 Register Definitions
    • 2.14.1 PCI Configuration Registers
      • Figure 15. ATU Interface Configuration Header Format
      • Figure 16. ATU Interface Extended Configuration Header Format (Power Management)
      • Figure 17. ATU Interface Extended Configuration Header Format (MSI-X Capability)
      • Figure 18. ATU Interface Extended Configuration Header Format (MSI Capability)
      • Figure 19. ATU Interface Extended Configuration Header Format (PCI-X Capability Type 1)
      • Figure 20. ATU Extended Configuration Header Format (Compact PCI Hot-Swap Capability)
      • Figure 21. ATU Interface Extended Configuration Header Format (VPD Capability)
    • 2.14.2 Internal Bus Registers
      • Table 26. Address Translation Unit Registers (Sheet 1 of 3)
      • Table 27. ATU Internal Bus Memory Mapped Register Range Offsets
      • Table 28. PCI-X Pad Registers
    • 2.14.3 ATU Vendor ID Register - ATUVID
      • Table 29. ATU Vendor ID Register - ATUVID
    • 2.14.4 ATU Device ID Register - ATUDID
      • Table 30. ATU Device ID Register - ATUDID
    • 2.14.5 ATU Command Register - ATUCMD
      • Table 31. ATU Command Register - ATUCMD
    • 2.14.6 ATU Status Register - ATUSR
      • Table 32. ATU Status Register - ATUSR (Sheet 1 of 2)
    • 2.14.7 ATU Revision ID Register - ATURID
      • Table 33. ATU Revision ID Register - ATURID
    • 2.14.8 ATU Class Code Register - ATUCCR
      • Table 34. ATU Class Code Register - ATUCCR
    • 2.14.9 ATU Cacheline Size Register - ATUCLSR
      • Table 35. ATU Cacheline Size Register - ATUCLSR
    • 2.14.10 ATU Latency Timer Register - ATULT
      • Table 36. ATU Latency Timer Register - ATULT
    • 2.14.11 ATU Header Type Register - ATUHTR
      • Table 37. ATU Header Type Register - ATUHTR
    • 2.14.12 ATU BIST Register - ATUBISTR
      • Table 38. ATU BIST Register - ATUBISTR
    • 2.14.13 Inbound ATU Base Address Register 0 - IABAR0
      • Table 39. Inbound ATU Base Address Register 0 - IABAR0
    • 2.14.14 Inbound ATU Upper Base Address Register 0 - IAUBAR0
      • Table 40. Inbound ATU Upper Base Address Register 0 - IAUBAR0
    • 2.14.15 Inbound ATU Base Address Register 1 - IABAR1
      • Table 41. Inbound ATU Base Address Register 1 - IABAR1
    • 2.14.16 Inbound ATU Upper Base Address Register 1 - IAUBAR1
      • Table 42. Inbound ATU Upper Base Address Register 1 - IAUBAR1
    • 2.14.17 Inbound ATU Base Address Register 2 - IABAR2
      • Table 43. Inbound ATU Base Address Register 2 - IABAR2
    • 2.14.18 Inbound ATU Upper Base Address Register 2 - IAUBAR2
      • Table 44. Inbound ATU Upper Base Address Register 2 - IAUBAR2
    • 2.14.19 ATU Subsystem Vendor ID Register - ASVIR
      • Table 45. ATU Subsystem Vendor ID Register - ASVIR
    • 2.14.20 ATU Subsystem ID Register - ASIR
      • Table 46. ATU Subsystem ID Register - ASIR
    • 2.14.21 Expansion ROM Base Address Register - ERBAR
      • Table 47. Expansion ROM Base Address Register -ERBAR
    • 2.14.22 ATU Capabilities Pointer Register - ATU_Cap_Ptr
      • Table 48. ATU Capabilities Pointer Register - ATU_Cap_Ptr
    • 2.14.23 Determining Block Sizes for Base Address Registers
      • Table 49. Memory Block Size Read Response
      • Table 50. ATU Base Registers and Associated Limit Registers
    • 2.14.24 ATU Interrupt Line Register - ATUILR
      • Table 51. ATU Interrupt Line Register - ATUILR
    • 2.14.25 ATU Interrupt Pin Register - ATUIPR
      • Table 52. ATU Interrupt Pin Register - ATUIPR
    • 2.14.26 ATU Minimum Grant Register - ATUMGNT
      • Table 53. ATU Minimum Grant Register - ATUMGNT
    • 2.14.27 ATU Maximum Latency Register - ATUMLAT
      • Table 54. ATU Maximum Latency Register - ATUMLAT
    • 2.14.28 Inbound ATU Limit Register 0 - IALR0
      • Table 55. Inbound ATU Limit Register 0 - IALR0
    • 2.14.29 Inbound ATU Translate Value Register 0 - IATVR0
      • Table 56. Inbound ATU Translate Value Register 0 - IATVR0
    • 2.14.30 Inbound ATU Upper Translate Value Register 0 - IAUTVR0
      • Table 57. Inbound ATU Upper Translate Value Register 0 - IAUTVR0
    • 2.14.31 Inbound ATU Limit Register 1 - IALR1
      • Table 58. Inbound ATU Limit Register 1 - IALR1
    • 2.14.32 Inbound ATU Translate Value Register 1 - IATVR1
      • Table 59. Inbound ATU Translate Value Register 1 - IATVR1
    • 2.14.33 Inbound ATU Upper Translate Value Register 1 - IAUTVR1
      • Table 60. Inbound ATU Upper Translate Value Register 1 - IAUTVR1
    • 2.14.34 Inbound ATU Limit Register 2 - IALR2
      • Table 61. Inbound ATU Limit Register 2 - IALR2
    • 2.14.35 Inbound ATU Translate Value Register 2 - IATVR2
      • Table 62. Inbound ATU Translate Value Register 2 - IATVR2
    • 2.14.36 Inbound ATU Upper Translate Value Register 2 - IAUTVR2
      • Table 63. Inbound ATU Upper Translate Value Register 2 - IAUTVR2
    • 2.14.37 Expansion ROM Limit Register - ERLR
      • Table 64. Expansion ROM Limit Register - ERLR
    • 2.14.38 Expansion ROM Translate Value Register - ERTVR
      • Table 65. Expansion ROM Translate Value Register - ERTVR
    • 2.14.39 Expansion ROM Upper Translate Value Register - ERUTVR
      • Table 66. Expansion ROM Upper Translate Value Register - ERUTVR
    • 2.14.40 ATU Configuration Register - ATUCR
      • Table 67. ATU Configuration Register - ATUCR
    • 2.14.41 PCI Configuration and Status Register - PCSR
      • Table 68. PCI Configuration and Status Register - PCSR (Sheet 1 of 3)
    • 2.14.42 ATU Interrupt Status Register - ATUISR
      • Table 69. ATU Interrupt Status Register - ATUISR (Sheet 1 of 2)
    • 2.14.43 ATU Interrupt Mask Register - ATUIMR
      • Table 70. ATU Interrupt Mask Register - ATUIMR (Sheet 1 of 2)
    • 2.14.44 VPD Capability Identifier Register - VPD_Cap_ID
      • Table 71. VPD Capability Identifier Register - VPD_Cap_ID
    • 2.14.45 VPD Next Item Pointer Register - VPD_Next_Item_Ptr
      • Table 72. VPD Next Item Pointer Register - VPD_Next_Item_Ptr
    • 2.14.46 VPD Address Register - VPDAR
      • Table 73. VPD Address Register - VPDAR
    • 2.14.47 VPD Data Register - VPDDR
      • Table 74. VPD Data Register - VPDDR
    • 2.14.48 PM Capability Identifier Register - PM_Cap_ID
      • Table 75. PM_Capability Identifier Register - PM_Cap_ID
    • 2.14.49 PM Next Item Pointer Register - PM_Next_Item_Ptr
      • Table 76. PM Next Item Pointer Register - PM_Next_Item_Ptr
    • 2.14.50 ATU Power Management Capabilities Register - APMCR
      • Table 77. ATU Power Management Capabilities Register - APMCR
    • 2.14.51 ATU Power Management Control/Status Register - APMCSR
      • Table 78. ATU Power Management Control/Status Register - APMCSR
    • 2.14.52 ATU Scratch Pad Register - ATUSPR
      • Table 79. Scratch Pad Register - ATUSPR
    • 2.14.53 PCI-X Capability Identifier Register - PCI-X_Cap_ID
      • Table 80. PCI-X_Capability Identifier Register - PCI-X_Cap_ID
    • 2.14.54 PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr
      • Table 81. PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr
    • 2.14.55 PCI-X Command Register - PCIXCMD
      • Table 82. PCI-X Command Register - PCIXCMD (Sheet 1 of 2)
    • 2.14.56 PCI-X Status Register - PCIXSR
      • Table 83. PCI-X Status Register - PCIXSR (Sheet 1 of 2)
    • 2.14.57 ECC Control and Status Register - ECCCSR
      • Table 84. ECC Control and Status Register - ECCCSR (Sheet 1 of 3)
    • 2.14.58 ECC First Address Register - ECCFAR
      • Table 85. ECC First Address Register - ECCFAR
    • 2.14.59 ECC Second Address Register - ECCSAR
      • Table 86. ECC Second Address Register - ECCSAR
    • 2.14.60 ECC Attribute Register - ECCAR
      • Table 87. ECC Attribute Register - ECCAR
    • 2.14.61 CompactPCI Hot-Swap Capability ID Register
      • Table 88. HS_CAPID - Hot-Swap Cap ID
    • 2.14.62 Offset EDh: HS_NXTP - Next Item Pointer
      • Table 89. HS_NXTP - Next Item Pointer
    • 2.14.63 HS_CNTRL - Hot-Swap Control/Status Register
      • Table 90. HS_CNTRL - Hot-Swap Control/Status Register (Sheet 1 of 2)
    • 2.14.64 Inbound ATU Base Address Register 3 - IABAR3
      • Table 91. Inbound ATU Base Address Register 3 - IABAR3
    • 2.14.65 Inbound ATU Upper Base Address Register 3 - IAUBAR3
      • Table 92. Inbound ATU Upper Base Address Register 3 - IAUBAR3
    • 2.14.66 Inbound ATU Limit Register 3 - IALR3
      • Table 93. Inbound ATU Limit Register 3 - IALR3
    • 2.14.67 Inbound ATU Translate Value Register 3 - IATVR3
      • Table 94. Inbound ATU Translate Value Register 3 - IATVR3
    • 2.14.68 Inbound ATU Upper Translate Value Register 3 - IAUTVR3
      • Table 95. Inbound ATU Upper Translate Value Register 3 - IAUTVR3
    • 2.14.69 Outbound I/O Base Address Register - OIOBAR
      • Table 96. Outbound I/O Base Address Register - OIOBAR
    • 2.14.70 Outbound I/O Window Translate Value Register - OIOWTVR
      • Table 97. Outbound I/O Window Translate Value Register - OIOWTVR
    • 2.14.71 Outbound Upper Memory Window Base Address Register 0 - OUMBAR0
      • Table 98. Outbound Upper Memory Window Base Address Register 0 - OUMBAR0
    • 2.14.72 Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
      • Table 99. Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0
    • 2.14.73 Outbound Upper Memory Window Base Address Register 1 - OUMBAR1
      • Table 100. Outbound Upper Memory Window Base Address Register 1 - OUMBAR1
    • 2.14.74 Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
      • Table 101. Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1
    • 2.14.75 Outbound Upper Memory Window Base Address Register 2 - OUMBAR2
      • Table 102. Outbound Upper Memory Window Base Address Register 2- OUMBAR2
    • 2.14.76 Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2
      • Table 103. Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2
    • 2.14.77 Outbound Upper Memory Window Base Address Register 3 - OUMBAR3
      • Table 104. Outbound Upper Memory Window Base Address Register 3 - OUMBAR3
    • 2.14.78 Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3
      • Table 105. Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3
    • 2.14.79 Outbound Configuration Cycle Address Register - OCCAR
      • Table 106. Outbound Configuration Cycle Address Register - OCCAR
    • 2.14.80 Outbound Configuration Cycle Data Register - OCCDR
      • Table 107. Outbound Configuration Cycle Data Register - OCCDR
    • 2.14.81 Outbound Configuration Cycle Function Number - OCCFN
      • Table 108. Outbound Configuration Cycle Function Number Register - OCCFN
    • 2.14.82 PCI Interface Error Control and Status Register - PIECSR
      • Table 109. PCI Interface Error Control and Status Register - PIECSR
    • 2.14.83 PCI Interface Error Address Register - PCIEAR
      • Table 110. PCI Interface Error Address Register - PCIEAR
    • 2.14.84 PCI Interface Error Upper Address Register - PCIEUAR
      • Table 111. PCI Interface Error Upper Address Register - PCIEUAR
    • 2.14.85 PCI Interface Error Context Address Register - PCIECAR
      • Table 112. PCI Interface Error Context Address Register - PCIECAR
    • 2.14.86 Internal Arbiter Control Register - IACR
      • Table 113. Internal Arbiter Control Register - IACR
    • 2.14.87 Multi-Transaction Timer - MTT
      • Table 114. Multi-Transaction Timer - MTT
    • 2.14.88 PCIX RCOMP Control Register - PRCR
      • Table 115. PCIX RCOMP Control Register - PRCR
    • 2.14.89 PCIX Pad ODT Drive Strength Manual Override Values Registers - PPODSMOVR
      • Table 116. PCIX Pad ODT Drive Strength Manual Override Values Registers - PPODSMOVR
    • 2.14.90 PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V/1.5 V Switch Supply Voltage) - PPDSMOVR3.3_1.5
      • Table 117. PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3V/1.5V Switch Supply Voltage) - PPDSMOVR3.3_1.5
    • 2.14.91 PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage) - PPDSMOVR3.3
      • Table 118. PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage) - PPDSMOVR3.3
• 3.0 Address Translation Unit (PCI Express)
  • 3.1 Overview
    • Figure 22. ATU Block Diagram
    • Figure 23. ATU Queue Architecture Block Diagram
  • 3.2 PCI Express Link Characteristics
  • 3.3 ATU Address Translation
    • Table 119. Supported Address Spaces and Transaction Types
    • Table 120. ATU Command Support
    • 3.3.1 Inbound Transactions
      • 3.3.1.1 Inbound Address Translation
        • Equation 8. Inbound Address Detection
        • Figure 24. Inbound Address Detection
        • Equation 9. Inbound Translation
        • Figure 25. Inbound Translation Example
      • 3.3.1.2 Inbound Memory Write Transaction
      • 3.3.1.3 Inbound Memory Read Transaction
      • 3.3.1.4 Inbound I/O Cycle Translation
      • 3.3.1.5 Inbound Configuration Cycle Translation (ID Routed)
      • 3.3.1.6 Inbound Vendor_Defined Message Transactions
        • Table 121. Inbound Vendor_Defined Message Type 0 Response.
    • 3.3.2 Outbound Transactions
      • 3.3.2.1 Outbound Address Translation - Internal Bus Transactions
        • Table 122. Outbound Address Translation Control
      • 3.3.2.2 Outbound Address Translation Windows
        • Table 123. Internal Bus-to-PCI Command Translation for Memory Windows
        • Table 124. Internal Bus-to-PCI Command Translation for I/O Window
        • Figure 26. 4 Gbyte Section 0 of the Internal Bus Memory Map
        • Equation 10. Outbound Address Translation
        • Equation 11. I/O Transactions
        • Figure 27. Outbound Address Translation Windows
      • 3.3.2.3 Outbound DMA Transactions
      • 3.3.2.4 Outbound Function Number
    • 3.3.3 Outbound Write Transaction
    • 3.3.4 Outbound Read Transaction
    • 3.3.5 Outbound Configuration Cycle Translation
      • 3.3.5.1 Outbound Configuration Cycle Error Conditions
      • 3.3.5.2 Outbound Configuration Completions with Retry Status (CRS)
      • 3.3.5.3 Outbound PCI Express Message Transactions
      • 3.3.5.4 Completion Timeout Mechanism
  • 3.4 Big Endian Byte Swapping
    • 3.4.1 Inbound Byte Swapping
      • Figure 28. Inbound Byte Swapping
    • 3.4.2 Outbound Byte Swapping
      • Figure 29. Outbound Byte Swapping for Transaction with Byte Count of 1
      • Figure 30. Outbound Byte Swapping for Transactions with Byte Count of 2
      • Figure 31. Outbound Byte Swapping Transaction with Byte Count of 3 or Larger
  • 3.5 Messaging Unit
  • 3.6 PCI Express Messages
    • Table 125. Supported Message Types (Sheet 1 of 2)
  • 3.7 Expansion ROM Translation Unit
  • 3.8 ATU Queue Architecture
    • 3.8.1 Inbound Queues
      • Table 126. Inbound Queues
      • 3.8.1.1 Inbound Posted Queue Structure
      • 3.8.1.2 Inbound Non Posted Queue Structure
      • 3.8.1.3 Inbound Completion Queue Structure
      • 3.8.1.4 Inbound Transaction Queues Command Translation Summary
        • Table 127. PCI to Internal Bus Command Translation for All Inbound Transactions
    • 3.8.2 Outbound Queues
      • Table 128. Outbound Queues
      • 3.8.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes
    • 3.8.3 Transaction Ordering
      • Table 129. ATU Inbound Data Flow Ordering Rules
      • Table 130. ATU Outbound Data Flow Ordering Rules
      • 3.8.3.1 Transaction Ordering Summary
        • Table 131. Inbound Transaction Ordering Summary
        • Table 132. Outbound Transaction Ordering Summary
    • 3.8.4 Byte Parity Checking and Generation
      • 3.8.4.1 Parity Generation
        • Equation 12. DATAP0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]
        • Table 133. Parity Generation
      • 3.8.4.2 Parity Checking
        • Equation 13. PARITY_RESULT = ADDP0 XOR A[0] XOR A[1] XOR A[2] XOR A[3] XOR A[4] XOR A[5] XOR A[6] XOR A[7]
        • Equation 14. PARITY_RESULT = DATAP0 XOR D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]
      • 3.8.4.3 Parity Disabled
  • 3.9 ATU Error Conditions
    • 3.9.1 PCI Express Errors
      • 3.9.1.1 Role Based Error Reporting
        • Table 134. Advisory Error Cases
      • 3.9.1.2 Malformed Packets
      • 3.9.1.3 ECRC Check Failed
      • 3.9.1.4 Unsupported Request
      • 3.9.1.5 Completer Abort
      • 3.9.1.6 Unexpected Completions
      • 3.9.1.7 Poisoned TLP Received
      • 3.9.1.8 Completion Timeout
    • 3.9.2 Parity Error on the Internal Bus
    • 3.9.3 ATU Error Summary
      • Table 135. PCI Express Error Summary (Sheet 1 of 2)
      • Table 136. Root Complex Error Summary
      • Table 137. Internal Bus Error Summary
  • 3.10 PCI Express Hot-Plug Support
  • 3.11 Reset
  • 3.12 Message-Signaled Interrupts
    • 3.12.1 Legacy Interrupts
    • 3.12.2 Internal Interrupts
  • 3.13 Vital Product Data
    • 3.13.1 Configuring Vital Product Data Operation
    • 3.13.2 Accessing Vital Product Data
      • 3.13.2.1 Reading Vital Product Data
      • 3.13.2.2 Writing Vital Product Data
  • 3.14 Multi-Function Support
    • 3.14.1 PCI Express Interface Control Parameters
      • Table 138. PCI Express Interface Control Parameters Usage (Sheet 1 of 2)
    • 3.14.2 PCI Express Interface Status Reporting
      • Table 139. PCI Express Interface Status Reporting Usage
  • 3.15 Root Complex Functionality
  • 3.16 Embedded Bridge Functionality
  • 3.17 Register Definitions
    • Figure 32. ATU Interface Configuration Header Format
    • 3.17.1 Extended Capabilities Registers
      • Figure 33. ATU Interface Extended Configuration Header Format (Power Management)
      • Figure 34. ATU Interface Extended Configuration Header Format (MSI-X Capability)
      • Figure 35. ATU Interface Extended Configuration Header Format (MSI Capability)
      • Figure 36. ATU Interface Extended Configuration Header Format (PCI Express Capability)
      • Figure 37. ATU Interface Extended Configuration Header Format (VPD Capability)
    • 3.17.2 Internal Bus Addresses
      • Table 140. ATU Internal Bus Memory Mapped Register Range Offsets
      • Table 141. ATU PCI Configuration Register Space (Sheet 1 of 3)
    • 3.17.3 ATU Vendor ID Register - ATUVID
      • Table 142. ATU Vendor ID Register - ATUVID
    • 3.17.4 ATU Device ID Register - ATUDID
      • Table 143. ATU Device ID Register - ATUDID
    • 3.17.5 ATU Command Register - ATUCMD
      • Table 144. ATU Command Register - ATUCMD
    • 3.17.6 ATU Status Register - ATUSR
      • Table 145. ATU Status Register - ATUSR
    • 3.17.7 ATU Revision ID Register - ATURID
      • Table 146. ATU Revision ID Register - ATURID
    • 3.17.8 ATU Class Code Register - ATUCCR
      • Table 147. ATU Class Code Register - ATUCCR
    • 3.17.9 ATU Cacheline Size Register - ATUCLSR
      • Table 148. ATU Cacheline Size Register - ATUCLSR
    • 3.17.10 ATU Latency Timer Register - ATULT
      • Table 149. ATU Latency Timer Register - ATULT
    • 3.17.11 ATU Header Type Register - ATUHTR
      • Table 150. ATU Header Type Register - ATUHTR
    • 3.17.12 ATU BIST Register - ATUBISTR
      • Table 151. ATU BIST Register - ATUBISTR
    • 3.17.13 Inbound ATU Base Address Register 0 - IABAR0
      • Table 152. Inbound ATU Base Address Register 0 - IABAR0
    • 3.17.14 Inbound ATU Upper Base Address Register 0 - IAUBAR0
      • Table 153. Inbound ATU Upper Base Address Register 0 - IAUBAR0
    • 3.17.15 Determining Block Sizes for Base Address Registers
      • Table 154. Memory Block Size Read Response
      • Table 155. ATU Base Registers and Associated Limit Registers
    • 3.17.16 Inbound ATU Base Address Register 1 - IABAR1
      • Table 156. Inbound ATU Base Address Register 1 - IABAR1
    • 3.17.17 Inbound ATU Upper Base Address Register 1 - IAUBAR1
      • Table 157. Inbound ATU Upper Base Address Register 1 - IAUBAR1
    • 3.17.18 Inbound ATU Base Address Register 2 - IABAR2
      • Table 158. Inbound ATU Base Address Register 2 - IABAR2
    • 3.17.19 Inbound ATU Upper Base Address Register 2 - IAUBAR2
      • Table 159. Inbound ATU Upper Base Address Register 2 - IAUBAR2
    • 3.17.20 ATU Subsystem Vendor ID Register - ASVIR
      • Table 160. ATU Subsystem Vendor ID Register - ASVIR
    • 3.17.21 ATU Subsystem ID Register - ASIR
      • Table 161. ATU Subsystem ID Register - ASIR
    • 3.17.22 Expansion ROM Base Address Register - ERBAR
      • Table 162. Expansion ROM Base Address Register -ERBAR
    • 3.17.23 ATU Capabilities Pointer Register - ATU_Cap_Ptr
      • Table 163. ATU Capabilities Pointer Register - ATU_Cap_Ptr
    • 3.17.24 ATU Interrupt Line Register - ATUILR
      • Table 164. ATU Interrupt Line Register - ATUILR
    • 3.17.25 ATU Interrupt Pin Register - ATUIPR
      • Table 165. ATU Interrupt Pin Register - ATUIPR
    • 3.17.26 ATU Minimum Grant Register - ATUMGNT
      • Table 166. ATU Minimum Grant Register - ATUMGNT
    • 3.17.27 ATU Maximum Latency Register - ATUMLAT
      • Table 167. ATU Maximum Latency Register - ATUMLAT
    • 3.17.28 Inbound ATU Limit Register 0 - IALR0
      • Table 168. Inbound ATU Limit Register 0 - IALR0
    • 3.17.29 Inbound ATU Translate Value Register 0 - IATVR0
      • Table 169. Inbound ATU Translate Value Register 0 - IATVR0
    • 3.17.30 Inbound ATU Upper Translate Value Register 0 - IAUTVR0
      • Table 170. Inbound ATU Upper Translate Value Register 0 - IAUTVR0
    • 3.17.31 Inbound ATU Limit Register 1 - IALR1
      • Table 171. Inbound ATU Limit Register 1 - IALR1
    • 3.17.32 Inbound ATU Translate Value Register 1 - IATVR1
      • Table 172. Inbound ATU Translate Value Register 1 - IATVR1
    • 3.17.33 Inbound ATU Upper Translate Value Register 1 - IAUTVR1
      • Table 173. Inbound ATU Upper Translate Value Register 1 - IAUTVR1
    • 3.17.34 Inbound ATU Limit Register 2 - IALR2
      • Table 174. Inbound ATU Limit Register 2 - IALR2
    • 3.17.35 Inbound ATU Translate Value Register 2 - IATVR2
      • Table 175. Inbound ATU Translate Value Register 2 - IATVR2
    • 3.17.36 Inbound ATU Upper Translate Value Register 2 - IAUTVR2
      • Table 176. Inbound ATU Upper Translate Value Register 2 - IAUTVR2
    • 3.17.37 Expansion ROM Limit Register - ERLR
      • Table 177. Expansion ROM Limit Register - ERLR
    • 3.17.38 Expansion ROM Translate Value Register - ERTVR
      • Table 178. Expansion ROM Translate Value Register - ERTVR
    • 3.17.39 Expansion ROM Upper Translate Value Register - ERUTVR
      • Table 179. Expansion ROM Upper Translate Value Register - ERUTVR
    • 3.17.40 ATU Configuration Register - ATUCR
      • Table 180. ATU Configuration Register - ATUCR
    • 3.17.41 PCI Configuration and Status Register - PCSR
      • Table 181. PCI Configuration and Status Register - PCSR (Sheet 1 of 2)
    • 3.17.42 ATU Interrupt Status Register - ATUISR
      • Table 182. ATU Interrupt Status Register - ATUISR (Sheet 1 of 3)
    • 3.17.43 ATU Interrupt Mask Register - ATUIMR
      • Table 183. ATU Interrupt Mask Register - ATUIMR
    • 3.17.44 PCI Express Message Control/Status Register - PEMCSR
      • Table 184. PCI Express Message Control and Status Register - PEMCSR
    • 3.17.45 PCI Express Link Control/Status Register - PELCSR
      • Table 185. PCI Express Link Control and Status Register - PELCSR
    • 3.17.46 VPD Capability Identifier Register - VPD_Cap_ID
      • Table 186. VPD Capability Identifier Register - VPD_Cap_ID
    • 3.17.47 VPD Next Item Pointer Register - VPD_Next_Item_Ptr
      • Table 187. VPD Next Item Pointer Register - VPD_Next_Item_Ptr
    • 3.17.48 VPD Address Register - VPDAR
      • Table 188. VPD Address Register - VPDAR
    • 3.17.49 VPD Data Register - VPDDR
      • Table 189. VPD Data Register - VPDDR
    • 3.17.50 PM Capability Identifier Register - PM_Cap_ID
      • Table 190. PM_Capability Identifier Register - PM_Cap_ID
    • 3.17.51 PM Next Item Pointer Register - PM_Next_Item_Ptr
      • Table 191. PM Next Item Pointer Register - PM_Next_Item_Ptr
    • 3.17.52 ATU Power Management Capabilities Register - APMCR
      • Table 192. ATU Power Management Capabilities Register - APMCR
    • 3.17.53 ATU Power Management Control/Status Register - APMCSR
      • Table 193. ATU Power Management Control/Status Register - APMCSR
    • 3.17.54 ATU Scratch Pad Register - ATUSPR
      • Table 194. Scratch Pad Register - ATUSPR
    • 3.17.55 PCI Express Capability List Register - PCIE_CAPID
      • Table 195. PCI Express Capability Identifier Register - PCIE_CAPID
    • 3.17.56 PCI Express Next Item Pointer Register - PCIE_NXTP
      • Table 196. PCI Express Next Item Pointer Register - PCIE_NXTP
    • 3.17.57 PCI Express Capabilities Register - PCIE_CAP
      • Table 197. PCI Express Capabilities Register PCIE_CAP
    • 3.17.58 PCI Express Device Capabilities Register - PCIE_DCAP
      • Table 198. PCI Express Device Capabilities Register - PCIE_DCAP
    • 3.17.59 PCI Express Device Control Register - PE_DCTL
      • Table 199. PCI Express Device Control Register - PE_DCTL (Sheet 1 of 2)
    • 3.17.60 PCI Express Device Status Register - PE_DSTS
      • Table 200. PCI Express Device Status Register PE_DSTS
    • 3.17.61 PCI Express Link Capabilities Register - PE_LCAP
      • Table 201. PCI Express Link Capabilities Register - PE_LCAP
    • 3.17.62 PCI Express Link Control Register - PE_LCTL
      • Table 202. PCI Express Link Control Register PE_LCTL
    • 3.17.63 PCI Express Link Status Register - PE_LSTS
      • Table 203. PCI Express Link Status Register PE_LSTS
    • 3.17.64 PCI Express Slot Capabilities Register - PE_SCAP
      • Table 204. PCI Express Slot Capabilities Register - PE_SCAP
    • 3.17.65 PCI Express Slot Control Register - PE_SCR
      • Table 205. PCI Express Slot Control Register PE_SCR
    • 3.17.66 PCI Express Slot Status Register - PE_SSTS
      • Table 206. PCI Express Slot Status Register PE_SSTS
    • 3.17.67 PCI Express Root Control Register - PE_RCR
      • Table 207. PCI Express Root Control Register - PE_RCR
    • 3.17.68 PCI Express Root Status Register - PE_RSR
      • Table 208. PCI Express Root Status Register PE_RSR
    • 3.17.69 PCI Express Advanced Error Capability Identifier - ADVERR_CAPID
      • Table 209. PCI Express Advanced Error Capability Identifier - ADVERR_CAPID
    • 3.17.70 PCI Express Uncorrectable Error Status - ERRUNC_STS
      • Table 210. PCI Express Uncorrectable Error Status - ERRUNC_STS
    • 3.17.71 PCI Express Uncorrectable Error Mask - ERRUNC_MSK
      • Table 211. PCI Express Uncorrectable Error Mask - ERRUNC_MSK
    • 3.17.72 PCI Express Uncorrectable Error Severity - ERRUNC_SEV
      • Table 212. PCI Express Uncorrectable Error Severity - ERRUNC_SEV
    • 3.17.73 PCI Express Correctable Error Status - ERRCOR_STS
      • Table 213. PCI Express Correctable Error Status - ERRCOR_STS
    • 3.17.74 PCI Express Correctable Error Mask - ERRCOR_MSK
      • Table 214. PCI Express Correctable Error Mask - ERRCOR_MSK
    • 3.17.75 Advanced Error Control and Capability Register - ADVERR_CTL
      • Table 215. Advanced Error Control and Capability Register - ADVERR_CTL
    • 3.17.76 PCI Express Advanced Error Header Log - ADVERR_LOG0
      • Table 216. PCI Express Advanced Error Header Log - ADVERR_LOG0
    • 3.17.77 PCI Express Advanced Error Header Log - ADVERR_LOG1
      • Table 217. PCI Express Advanced Error Header Log - ADVERR_LOG1
    • 3.17.78 PCI Express Advanced Error Header Log - ADVERR_LOG2
      • Table 218. PCI Express Advanced Error Header Log - ADVERR_LOG2
    • 3.17.79 PCI Express Advanced Error Header Log - ADVERR_LOG3
      • Table 219. PCI Express Advanced Error Header Log - ADVERR_LOG3
    • 3.17.80 Root Error Command Register - RERR_CMD
      • Table 220. Root Error Command Register - RERR_CMD
    • 3.17.81 Root Error Status Register
      • Table 221. Root Error Status Register - RERR_SR
    • 3.17.82 Error Source Identification Register - RERR_ID
      • Table 222. Error Source Identification Register RERR_ID
    • 3.17.83 Device Serial Number Capability - DSN_CAP
      • Table 223. Device Serial Number Capability - DSN_CAP
    • 3.17.84 Device Serial Number Lower DW Register - DSN_LDW
      • Table 224. Device Serial Number Lower DW Register - DSN_LDW
    • 3.17.85 Device Serial Number Upper DW Register - DSN_UDW
      • Table 225. Device Serial Number Upper DW Register - DSN_UDW
    • 3.17.86 PCI Express Advisory Error Control Register - PIE_AEC
      • Table 226. PCI Express Advisory Error Control Register PIE_AEC
    • 3.17.87 Power Budgeting Enhanced Capability Header - PWRBGT_CAPID
      • Table 227. Power Budgeting Enhanced Capability Header - PWRBGT_CAPID
    • 3.17.88 Power Budgeting Data Select Register - PWRBGT_DSEL
      • Table 228. Power Budgeting Data Select Register - PWRBGT_DSEL
    • 3.17.89 Power Budgeting Data Register - PWRBGT_DATA
      • Table 229. Power Budgeting Data Register - PWRBGT_DATA
    • 3.17.90 Power Budgeting Capability Register - PWRBGT_CAP
      • Table 230. Power Budgeting Capability Register - PWRBGT_CAP
    • 3.17.91 Power Budgeting Information Registers[0:23]-PWRBGT_INFO[0:23]
      • Table 231. Power Budgeting Information Registers[0:23]-PWRBGT_INFO[0:23]
    • 3.17.92 Outbound I/O Base Address Register - OIOBAR
      • Table 232. Outbound I/O Base Address Register - OIOBAR
    • 3.17.93 Outbound I/O Window Translate Value Register - OIOWTVR
      • Table 233. Outbound I/O Window Translate Value Register - OIOWTVR
    • 3.17.94 Outbound Upper Memory Window Base Address Register 0 - OUMBAR0
      • Table 234. Outbound Upper Memory Window Base Address Register 0 - OUMBAR0
    • 3.17.95 Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
      • Table 235. Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0
    • 3.17.96 Outbound Upper Memory Window Base Address Register 1 - OUMBAR1
      • Table 236. Outbound Upper Memory Window Base Address Register 1 - OUMBAR1
    • 3.17.97 Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
      • Table 237. Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1
    • 3.17.98 Outbound Upper Memory Window Base Address Register 2 - OUMBAR2
      • Table 238. Outbound Upper Memory Window Base Address Register 2- OUMBAR2
    • 3.17.99 Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2
      • Table 239. Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2
    • 3.17.100 Outbound Upper Memory Window Base Address Register 3 - OUMBAR3
      • Table 240. Outbound Upper Memory Window Base Address Register 3 - OUMBAR3
    • 3.17.101 Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3
      • Table 241. Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3
    • 3.17.102 Outbound Configuration Cycle Address Register - OCCAR
      • Table 242. Outbound Configuration Cycle Address Register - OCCAR
    • 3.17.103 Outbound Configuration Cycle Data Register - OCCDR
      • Table 243. Outbound Configuration Cycle Data Register - OCCDR
    • 3.17.104 Outbound Configuration Cycle Function Number - OCCFN
      • Table 244. Outbound Configuration Cycle Function Number - OCCFN
    • 3.17.105 Inbound Vendor Message Header Register 0 - IVMHR0
      • Table 245. Inbound Vendor Defined Message Header Register0 - IVMHR0
      • Figure 38. PCI Express Vendor_Defined Message Header
    • 3.17.106 Inbound Vendor Message Header Register 1 - IVMHR1
      • Table 246. Inbound Vendor Defined Message Header Register 1 - IVMHR1
    • 3.17.107 Inbound Vendor Message Header Register 2 - IVMHR2
      • Table 247. Inbound Vendor Defined Message Header Register 2 - IVMHR2
    • 3.17.108 Inbound Vendor Message Header Register 3 - IVMHR3
      • Table 248. Inbound Vendor Defined Message Header Register 3 - IVMHR3
    • 3.17.109 Inbound Vendor Message Payload Register - IVMPR
      • Table 249. Inbound Vendor Defined Message Payload Register - IVMPR
    • 3.17.110 Outbound Vendor Message Header Register 0 - OVMHR0
      • Table 250. Outbound Vendor Defined Message Header Register0 - OVMHR0
    • 3.17.111 Outbound Vendor Message Header Register 1 - OVMHR1
      • Table 251. Outbound Vendor Defined Message Header Register 1 - OVMHR1
    • 3.17.112 Outbound Vendor Message Header Register 2 - OVMHR2
      • Table 252. Outbound Vendor Defined Message Header Register 2 - OVMHR2
    • 3.17.113 Outbound Vendor Message Header Register 3 - OVMHR3
      • Table 253. Outbound Vendor Defined Message Header Register 3 - OVMHR3
    • 3.17.114 Outbound Vendor Message Payload Register - OVMPR
      • Table 254. Outbound Vendor Defined Message Payload Register - OVMPR
    • 3.17.115 PCI Interface Error Control and Status Register - PIE_CSR
      • Table 255. PCI Interface Error Control and Status Register - PIE_CSR
    • 3.17.116 PCI Interface Error Status - PIE_STS
      • Table 256. PCI Interface Error Status - PIE_STS
    • 3.17.117 PCI Interface Error Mask - PIE_MSK
      • Table 257. PCI Interface Error Mask - PIE_MSK
    • 3.17.118 PCI Interface Error Header Log - PIE_LOG0
      • Table 258. PCI Interface Error Header Log - PIE_LOG0
    • 3.17.119 PCI Interface Error Header Log 1 - PIE_LOG1
      • Table 259. PCI Interface Error Header Log 1 - PIE_LOG1
    • 3.17.120 PCI Interface Error Header Log 2 - PIE_LOG2
      • Table 260. PCI Interface Error Header Log 2 - PIE_LOG2
    • 3.17.121 PCI Interface Error Header Log - PIE_LOG3
      • Table 261. PCI Interface Error Header Log - PIE_LOG3
    • 3.17.122 PCI Interface Error Descriptor Log
      • Table 262. PCI Interface Error Descriptor Log - PIE_DLOG
    • 3.17.123 ATU Reset Control Register - ATURCR
      • Table 263. ATU Reset Control Register - ATURCR
• 4.0 Messaging Unit
  • 4.1 Overview
  • 4.2 Theory of Operation
    • Figure 39. PCI Memory Map
    • Figure 40. Internal Bus Memory Map
    • Table 264. MU Summary
    • 4.2.1 Transaction Ordering
  • 4.3 Message Registers
    • 4.3.1 Outbound Messages
    • 4.3.2 Inbound Messages
  • 4.4 Doorbell Registers
    • 4.4.1 Outbound Doorbells
    • 4.4.2 Inbound Doorbells
  • 4.5 Messaging Unit Error Conditions
  • 4.6 Message-Signaled Interrupts
    • 4.6.1 MSI Capability Structure
    • 4.6.2 MSI-X Capability and Table Structures
      • Figure 41. MSI-X Table and PBA Address Mapping Layout relative to the Host Interface
      • Figure 42. MSI-X Table and PBA Address Mapping Layout relative to the Internal Bus
    • 4.6.3 Level-Triggered Versus Edge-Triggered Interrupts
  • 4.7 Register Definitions
    • Table 265. Message Unit Registers
    • 4.7.1 Inbound Message Register - IMRx
      • Table 266. Inbound Message Register - IMRx
    • 4.7.2 Outbound Message Register - OMRx
      • Table 267. Outbound Message Register - OMRx
    • 4.7.3 Inbound Doorbell Register - IDR
      • Table 268. Inbound Doorbell Register - IDR
    • 4.7.4 Inbound Interrupt Status Register - IISR
      • Table 269. Inbound Interrupt Status Register - IISR
    • 4.7.5 Inbound Interrupt Mask Register - IIMR
      • Table 270. Inbound Interrupt Mask Register - IIMR
    • 4.7.6 Outbound Doorbell Register - ODR
      • Table 271. Outbound Doorbell Register - ODR
    • 4.7.7 Outbound Interrupt Status Register - OISR
      • Table 272. Outbound Interrupt Status Register - OISR
    • 4.7.8 Outbound Interrupt Mask Register - OIMR
      • Table 273. Outbound Interrupt Mask Register - OIMR
    • 4.7.9 Inbound Reset Control and Status Register - IRCSR
      • Table 274. Inbound Reset Control and Status Register - IRCSR
    • 4.7.10 Outbound Reset Control and Status Register - ORCSR
      • Table 275. Outbound Reset Control and Status Register - ORCSR
    • 4.7.11 MSI Inbound Message Register - MIMR
      • Table 276. MSI Inbound Message Register - MIMR
    • 4.7.12 MU Configuration Register - MUCR
      • Table 277. MU Configuration Register - MUCR
    • 4.7.13 MU Base Address Register - MUBAR
      • Table 278. MU Base Address Register - MUBAR
    • 4.7.14 MU Upper Base Address Register - MUUBAR
      • Table 279. MU Upper Base Address Register - MUUBAR
    • 4.7.15 MU MSI-X Table Message Address Registers - M_MT_MAR[0:7]
      • Table 280. MU MSI-X Table Message Address Registers - M_MT_MAR [0:7]
    • 4.7.16 MU MSI-X Table Message Upper Address Registers - M_MT_MUAR[0:7]
      • Table 281. MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]
    • 4.7.17 MU MSI-X Table Message Data Registers - M_MT_MDR[0:7]
      • Table 282. MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]
    • 4.7.18 MU MSI-X Table Message Vector Control Registers - M_MT_MVCR[0:7]
      • Table 283. MU MSI-X Table Message Vector Control Registers - M_MT_MVCR [0:7]
    • 4.7.19 MU MSI-X Pending Bits Array Register - M_MPBAR
      • Table 284. MU MSI-X Pending Bits Array Register - M_MPBAR
    • 4.7.20 MSI Capability Identifier Register - Cap_ID
      • Table 285. MSI Capability Identifier Register - MSI_Cap_ID
    • 4.7.21 MSI Next Item Pointer Register - MSI_Next_Ptr
      • Table 286. MSI Next Item Pointer Register - MSI_Next_Ptr
    • 4.7.22 Message Control Register - Message_Control
      • Table 287. Message Control Register - Message_Control
    • 4.7.23 Message Address Register - Message_Address
      • Table 288. Message Address Register - Message_Address
    • 4.7.24 Message Upper Address Register - Message_Upper_Address
      • Table 289. Message Upper Address Register - Message_Upper_Address
    • 4.7.25 Message Data Register- Message_Data
      • Table 290. Message Data Register - Message_Data
    • 4.7.26 MSI-X Capability Identifier Register - MSI-X_Cap_ID
      • Table 291. MSI-X_Capability Identifier Register - MSI-X_Cap_ID
    • 4.7.27 MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr
      • Table 292. MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr
    • 4.7.28 MSI-X Message Control Register - MSI-X_MCR
      • Table 293. MSI-X Message Control Register - MSI-X_MCR
    • 4.7.29 MSI-X Table Offset Register - MSI-X_Table_Offset
      • Table 294. MSI-X Table Offset Register - MSI-X_Table_Offset
    • 4.7.30 MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset
      • Table 295. MSI-X Pending Bit Array Offset Register - MSI-X_PBA Offset
    • 4.7.31 MU MSI-X Control Register X - MMCRx
      • Table 296. MU MSI-X Control Register X - MMCRx
    • 4.7.32 Inbound MSI Interrupt Pending Register x - IMIPRx
      • Table 297. Inbound MSI Interrupt Pending Registers - IMIPR [0:3]
  • 4.8 Power/Default Status
• 5.0 SRAM DMA Unit (SDMA)
  • 5.1 Introduction
  • 5.2 Overview
  • 5.3 Theory of Operation
    • 5.3.1 Interrupt Control for SDMA
  • 5.4 Register Definitions
    • Table 298. SDMA Controller Unit Registers
    • 5.4.1 LocalToHost Destination Lower Address Register - L2H_DLAR
      • Table 299. LocalToHost Destination Lower Address Register - L2H_DLAR
    • 5.4.2 LocalToHost Destination Upper Address Register - L2H_DUAR
      • Table 300. LocalToHost Destination Upper Address Register - L2H_DUAR
    • 5.4.3 LocalToHost Source Lower Address Register - L2H_SLAR
      • Table 301. LocalToHost Source Lower Address Register - L2H_SLAR
    • 5.4.4 LocalToHost Byte Count Register - L2H_BCR
      • Table 302. LocalToHost Byte Count Register - L2H_BCR
    • 5.4.5 LocalToHost Interrupt Counter/Acknowledge Register L2H_ICAR
      • Table 303. LocalToHost Interrupt Counter/Acknowledge Register - L2H_ICAR
    • 5.4.6 LocalToHost Control/Status Register - L2H_CSR
      • Table 304. LocalToHost Control/Status Register - L2H_CSR
    • 5.4.7 LocalToHost Byte Swap Control Register - L2H_BSCR
      • Table 305. LocalToHost Byte Swap Control Register - L2H_BSCR
    • 5.4.8 HostToLocal Destination Lower Address Register - H2L_DLAR
      • Table 306. HostToLocal Destination Lower Address Register - H2L_DLAR
    • 5.4.9 HostToLocal Source Upper Address Register - H2L_SUAR
      • Table 307. HostToLocal Source Upper Address Register - H2L_SUAR
    • 5.4.10 HostToLocal Source Lower Address Register - H2L_SLAR
      • Table 308. HostToLocal Source Lower Address Register - H2L_SLAR
    • 5.4.11 HostToLocal Byte Count Register - H2L_BCR
      • Table 309. HostToLocal Byte Count Register - H2L_BCR
    • 5.4.12 HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR
      • Table 310. HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR
    • 5.4.13 HostToLocal Control/Status Register - H2L_CSR
      • Table 311. HostToLocal Control/Status Register - H2L_CSR
    • 5.4.14 HostToLocal Byte Swap Control Register - H2L_BSCR
      • Table 312. HostToLocal Byte Swap Control Register - H2L_BSCR
• 6.0 SGPIO Unit
  • 6.1 Overview
    • Figure 43. SGPIO Bus Overview
  • 6.2 Theory of Operation
    • Figure 44. SGPIO Repeating Bit Stream
    • 6.2.1 SGPIO SClock Output Signal
    • 6.2.2 SGPIO SLoad Output Signal
      • Figure 45. SLoad Signal
    • 6.2.3 SDataOut
      • Figure 46. SDataOut Signal
    • 6.2.4 SGPIO SDataIn Signal
      • Figure 47. SDataIn Signal
  • 6.3 Clock Requirements
    • Figure 48. Clock Structure
  • 6.4 Output Signals
    • Figure 49. SGPIO Output OD0 Signal
    • Figure 50. SGPIO Output OD1 Signal
    • Figure 51. SGPIO Output OD2 Signal
    • 6.4.1 Protocol Engine Input Signals
      • Table 313. SGPIO Input Mapping (Sheet 1 of 2)
      • 6.4.1.1 JOG Requirements
      • 6.4.1.2 Protocol Engine Pre-Conditioning Requirements
    • 6.4.2 Programmable Blink Patterns
  • 6.5 SGPIO Unit Mode of Operations
    • Figure 52. Output Signal Routing
    • Table 314. Example 1: Multiplexer Block Outputs for SGPIO Unit 0 in Direct LED Mode
    • Table 315. Example 2: Multiplexer Block Outputs for SGPIO Unit 1 in SGPIO Mode
    • Table 316. SGPIO Unit 0 Multiplexer Block Outputs for Example 2
    • Table 317. SGPIO Unit 1 Multiplexer Block Outputs for Example 2
    • 6.5.1 Pin Multiplexing
      • Table 318. SGPIO Unit 0 Pin Multiplexing
      • Figure 53. Intel® 413808 and 413812 I/O Controllers in TPER Mode SGPIO Unit 0 Pin Mapping
      • Table 319. SGPIO Unit 1 Pin Multiplexing
      • Figure 54. 4138xx SGPIO Unit 1 Pin Mapping
  • 6.6 Register Definitions
    • Table 320. SGPIO Memory-Mapped Rejecters
    • 6.6.1 SGPIO Interface Control Register x - SGICRx
      • Table 321. SGPIO Interface Control Register x - SGICRx
    • 6.6.2 SGPIO Programmable Blink Register x - SGPBRx
      • Table 322. SGPIO Programmable Blink Register x - SGPBRx (Sheet 1 of 2)
    • 6.6.3 SGPIO Start Drive Lower Register x - SGSDLRx
      • Table 323. SGPIO Start Drive Lower Register x - SGSDLRx (Sheet 1 of 2)
    • 6.6.4 SGPIO Start Drive Upper Register x - SGSDURx
      • Table 324. SGPIO Start Drive Upper Register x - SGSDURx (Sheet 1 of 2)
    • 6.6.5 SGPIO Serial Input Data Lower Register x - SGSIDLRx
      • Table 325. SGPIO Serial Input Data Lower Register x - SGSIDLRx
    • 6.6.6 SGPIO Serial Input Data Upper Register x - SGSIDURx
      • Table 326. SGPIO Serial Input Data Upper Register x - SGSIDURx
    • 6.6.7 SGPIO Vendor Specific Code Register x - SGVSCRx
      • Table 327. SGPIO Vendor Specific Code Register x - SGVSCRx
    • 6.6.8 SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x
      • Table 328. SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x
• 7.0 System Controller (SC) and Internal Bus Bridge
  • 7.1 Overview
  • 7.2 Theory of Operation
    • 7.2.1 System Controller
    • 7.2.2 Internal Bus Requester IDs
      • Table 329. Intel® 413808 and 413812 I/O Controllers in TPER Mode Initiator IDs
    • 7.2.3 Parity Testing
      • Figure 55. Typical Internal Bus System Controller Block Diagram
      • Table 330. Address and Data Parity Testing Initiator IDs
      • Table 331. Data Parity Testing Completer IDs
  • 7.3 Internal Bus Bridge
    • 7.3.1 Theory of Operation
    • 7.3.2 Internal Bus Commands
      • Table 332. Bridge supported Internal Bus Commands
    • 7.3.3 Transaction Queues
    • 7.3.4 Bridge Memory Window
    • 7.3.5 Ordering and Passing Rules
      • Table 333. Ordering and Passing Rules for both Inbound and Outbound Transactions
      • 7.3.5.1 Strong Ordering Rule Requirements
    • 7.3.6 Parity Support
      • 7.3.6.1 Address Parity Generation
      • 7.3.6.2 Address Parity Checking
      • 7.3.6.3 Data Parity on Outbound Transactions
      • 7.3.6.4 Data Parity on Inbound Transactions
    • 7.3.7 Error Detection and Handling
      • 7.3.7.1 Bridge North Internal Bus Interface Error
      • 7.3.7.2 Bridge South Internal Bus Interface Error
  • 7.4 System Controller Register Definitions
  • 7.5 Internal Bus Bridge Register Definitions
    • 7.5.1 Internal Bus Arbitration Control Register - IBACR
      • Table 334. Internal Bus Arbitration Control Register - IBACR (Sheet 1 of 2)
    • 7.5.2 South Internal Bus Address Test Control Register - SIBATCR
      • Table 335. South Internal Bus Address Test Control Register - SIBATCR
    • 7.5.3 South Internal Bus Data Test Control Register - SIBDTCR
      • Table 336. South Internal Bus Data Test Control Register - SIBDTCR
    • 7.5.4 Peripheral Memory-Mapped Register Base Address Register - PMMRBAR
      • Table 337. Peripheral Memory-Mapped Register Base Address Register - PMMRBAR
    • 7.5.5 Determining Block Sizes for Memory Windows
      • Table 338. Memory Block Size Limit Register Value
    • 7.5.6 Bridge Window Base Address Register - BWBAR
      • Table 339. Bridge Window Base Address Register - BWBAR
    • 7.5.7 Bridge Window Upper Base Address Register - BWUBAR
      • Table 340. Bridge Window Upper Base Address Register - BWUBAR
    • 7.5.8 Bridge Window Limit Register - BWLR
      • Table 341. Bridge Limit Register - BWLR
    • 7.5.9 Bridge Error Control and Status Register - BECSR
      • Table 342. Bridge Error Control and Status Register - BECSR (Sheet 1 of 2)
    • 7.5.10 Bridge Error Address Register - BERAR
      • Table 343. Bridge Error Address Register - BERAR
    • 7.5.11 Bridge Error Upper Address Register - BERUAR
      • Table 344. Bridge Error Upper Address Register - BERUAR
• 8.0 SRAM Memory Controller
  • 8.1 Overview
  • 8.2 Glossary
    • Table 345. Commonly Used Terms
  • 8.3 Theory of Operation
    • 8.3.1 Functional Block
      • Figure 56. Intel® 413808 and 413812 I/O Controllers in TPER Mode SRAM Memory Controller Block Diagram
      • 8.3.1.1 North Internal Bus Ports
      • 8.3.1.2 Address Decode Blocks
        • 8.3.1.2.1 SRAM Memory Array Space
        • 8.3.1.2.2 Memory-Mapped Register Space
        • 8.3.1.2.3 North Internal Bus Port Address Decode
      • 8.3.1.3 Memory Transaction Queues
        • 8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ)
      • 8.3.1.4 Configuration Registers
      • 8.3.1.5 SRAM Control Block
        • 8.3.1.5.1 SRAM State Machine and Pipeline Queues
        • 8.3.1.5.2 Error Correction Logic
      • 8.3.1.6 North Internal Bus Port Transaction Ordering
      • 8.3.1.7 SMCU Port Coherency
    • 8.3.2 SRAM Memory Interface Support
      • 8.3.2.1 SRAM Initialization
      • 8.3.2.2 SRAM Read Sequence
      • 8.3.2.3 SRAM Write Sequence
    • 8.3.3 Error Correction and Detection
      • 8.3.3.1 ECC Generation
        • Figure 57. ECC Write Flow
      • 8.3.3.2 ECC Generation for Partial Writes
        • Figure 58. Intel® 413808 and 413812 I/O Controllers G-Matrix (generates the ECC)
      • 8.3.3.3 ECC Checking
        • Table 346. Syndrome Decoding
        • Figure 59. ECC Read Data Flow
        • Figure 60. 4138xx H-Matrix (indicates the single-bit error location)
      • 8.3.3.4 Scrubbing
        • 8.3.3.4.1 ECC Example Using the H-Matrix
      • 8.3.3.5 ECC Disabled
      • 8.3.3.6 ECC Testing
    • 8.3.4 Byte Parity Checking and Generation
      • Figure 61. Logical Data Access Paths with Parity Protection
      • 8.3.4.1 Parity Generation
        • Equation 15. D_PARITY0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR BE[0]
        • Table 347. Data Parity Checking/Generation
      • 8.3.4.2 Parity Checking
        • Equation 16. DATA_PARITY_RESULT = D_PARITY0 XOR D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR BE[0]
      • 8.3.4.3 Parity Disabled
      • 8.3.4.4 Parity Testing
  • 8.4 ECC Interrupts/Error Conditions
    • Table 348. SMCU Error Response
    • 8.4.1 Single-Bit Error Detection
    • 8.4.2 Multi-bit Error Detection
  • 8.5 Parity Interrupts/Error Conditions
  • 8.6 Register Definitions
    • Table 349. Memory Controller Register
    • 8.6.1 SRAM Base Address Register - SRAMBAR
      • Table 350. SRAM Base Address Register - SRAMBAR
    • 8.6.2 SRAM Upper Base Address Register - SRAMUBAR
      • Table 351. SRAM Upper Base Address Register - SRAMUBAR
    • 8.6.3 SRAM ECC Control Register - SECR
      • Table 352. SRAM ECC Control Register - SECR
    • 8.6.4 SRAM ECC Log Register - SELOGR
      • Table 353. SRAM ECC Log Register - SELOG (Sheet 1 of 2)
    • 8.6.5 SRAM ECC Address Register - SEAR
      • Table 354. SRAM ECC Address Register - SEAR
    • 8.6.6 SRAM ECC Context Address Register - SECAR
      • Table 355. SRAM ECC Context Address Register - SECAR
    • 8.6.7 SRAM ECC Test Register - SECTST
      • Table 356. SRAM ECC Test Register - SECTST
    • 8.6.8 SRAM Parity Control and Status Register - SPARCSR
      • Table 357. SRAM Parity Control and Status Register - SPARCSR
    • 8.6.9 SRAM Parity Address Register - SPAR
      • Table 358. SRAM Parity Address Registers - SPAR
    • 8.6.10 SRAM Parity Upper Address Register - SPUAR
      • Table 359. SRAM Parity Upper Address Register - SPUAR
    • 8.6.11 SRAM Memory Controller Interrupt Status Register - SMCISR
      • Table 360. SRAM Memory Controller Interrupt Status Register - SMCISR
• 9.0 Peripheral Bus Interface Unit
  • Figure 62. The Peripheral Bus Interface Unit
  • 9.1 Overview
  • 9.2 Peripheral Bus Signals
    • 9.2.1 Address Signal Definitions
    • 9.2.2 Data Signal Definitions
    • 9.2.3 Control/Status Signal Definitions
    • 9.2.4 Bus Width
      • Figure 63. Data Width and Low Order Address Lines
    • 9.2.5 Detailed Signal Descriptions
      • Table 361. Bus Signal Descriptions
    • 9.2.6 Flash Memory Support
      • Figure 64. Sixty-Four Mbyte Flash Memory System
      • 9.2.6.1 Flash Read Cycle
        • Figure 65. 120 ns Flash Single Transfer Read Cycle
        • Figure 66. 120 ns Flash Burst Read Cycle
        • Table 362. Flash Wait State Profile Programming1
      • 9.2.6.2 Flash Write Cycle
        • Figure 67. 120 ns Flash Single Write Cycle1
  • 9.3 Register Definitions
    • Table 363. Peripheral Bus Interface Registers
    • 9.3.1 PBI Control Register - PBCR
      • Table 364. PBI Control Register - PBCR
    • 9.3.2 PBI Status Register - PBISR
      • Table 365. PBI Status Register - PBISR
    • 9.3.3 Determining Block Sizes for Memory Windows
      • Table 366. Memory Block Size Limit Register Values
    • 9.3.4 PBI Base Address Register 0 - PBBAR0
      • Table 367. PBI Base Address Register 0 - PBBAR0
    • 9.3.5 PBI Limit Register 0 - PBLR0
      • Table 368. PBI Limit Register 0 - PBLR0
    • 9.3.6 PBI Base Address Register 1 - PBBAR1
      • Table 369. PBI Base Address Register 1 - PBBAR1
    • 9.3.7 PBI Limit Register 1 - PBLR1
      • Table 370. PBI Limit Register 1 - PBLR1
    • 9.3.8 PBI Drive Strength Control Register - PBDSCR
      • Table 371. PBI Drive Strength Control Register - PBDSCR
    • 9.3.9 Processor Frequency Register - PFR
      • Table 372. Processor Frequency Register - PFR
    • 9.3.10 External Strap Status Register 0 - ESSTSR0
      • Table 373. External Strap Status Register 0 - ESSTS0
    • 9.3.11 Unique ID Register 0 - UID0
      • Table 374. Unique ID Register 0 - UID0
    • 9.3.12 Unique ID Register 1 - UID1
      • Table 375. Unique ID Register 1 - UID1
• 10.0 Interrupt Controller Unit
  • 10.1 Overview
  • 10.2 Theory of Operation
    • 10.2.1 Interrupt Controller Unit
  • 10.3 The Intel XScale® Processor Exceptions Architecture
    • 10.3.1 CPSR and SPSR
    • 10.3.2 The Exception Process
    • 10.3.3 Exception Priorities and Vectors
      • Table 376. Exception Priorities And Vectors
    • 10.3.4 Software Requirements For Exception Handling
      • 10.3.4.1 Nesting FIQ and IRQ Exceptions
  • 10.4 Intel® 413808 and 413812 I/O Controllers in TPER Mode External Interrupt Interface
    • 10.4.1 Interrupt Inputs
      • Table 377. Interrupt Input Pin Descriptions
    • 10.4.2 Outbound Interrupts
      • Table 378. Interrupt Output Pin Descriptions
  • 10.5 The Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Unit
    • 10.5.1 Programmer Model
      • 10.5.1.1 Active Interrupt Source Control and Status
        • Figure 68. Interrupt Controller Block Diagram (Active Interrupt Source Registers)
      • 10.5.1.2 Prioritization and Vector Generation for Active Interrupt Sources
        • Figure 69. Interrupt Controller Block Diagram (FIQ/IRQ Interrupt Vector Generation)
    • 10.5.2 Operational Blocks
      • Figure 70. Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Connections
    • 10.5.3 Intel® 413808 and 413812 I/O Controllers in TPER Mode: Internal Peripheral Interrupt
      • 10.5.3.1 Normal Interrupt Sources
        • Table 379. Normal Interrupt Sources
      • 10.5.3.2 Error Interrupt Sources
        • Table 380. Error Interrupt Sources
    • 10.5.4 High-Priority Interrupt (HPI#)
    • 10.5.5 Timer Interrupts
    • 10.5.6 Inter-Processor Interrupts
    • 10.5.7 Intel XScale® Processor Interrupts
    • 10.5.8 Software Interrupts
  • 10.6 Default Status
    • Table 381. Default Interrupt Routing and Status Values
  • 10.7 Interrupt Control Unit Registers
    • Table 382. Interrupt Controller Co-Processor Register Addresses (Sheet 1 of 2)
    • 10.7.1 Interrupt Base Register - INTBASE
      • Table 383. Interrupt Base Register - INTBASE
    • 10.7.2 Interrupt Size Register - INTSIZE
      • Table 384. Interrupt Size Register - INTSIZE
    • 10.7.3 IRQ Interrupt Vector Register - IINTVEC
      • Table 385. IRQ Interrupt Vector Register- IINTVEC
    • 10.7.4 FIQ Interrupt Vector Register - FINTVEC
      • Table 386. FIQ Interrupt Vector Register- FINTVEC
    • 10.7.5 Interrupt Pending Register 0 - INTPND0
      • Table 387. Interrupt Pending Register 0 - INTPND0
    • 10.7.6 Interrupt Pending Register 1 - INTPND1
      • Table 388. Interrupt Pending Register 1 - INTPND1
    • 10.7.7 Interrupt Pending Register 2 - INTPND2
      • Table 389. Interrupt Pending Register 2 - INTPND2
    • 10.7.8 Interrupt Pending Register 3 - INTPND3
      • Table 390. Interrupt Pending Register 3 - INTPND3
    • 10.7.9 Interrupt Control Register 0 - INTCTL0
      • Table 391. Interrupt Control Register 0 - INTCTL0 (Sheet 1 of 2)
    • 10.7.10 Interrupt Control Register 1 - INTCTL1
      • Table 392. Interrupt Control Register 1 - INTCTL1 (Sheet 1 of 2)
    • 10.7.11 Interrupt Control Register 2 - INTCTL2
      • Table 393. Interrupt Control Register 2 - INTCTL2
    • 10.7.12 Interrupt Control Register 3 - INTCTL3
      • Table 394. Interrupt Control Register 3 - INTCTL3 (Sheet 1 of 2)
    • 10.7.13 Interrupt Steering Register 0 - INTSTR0
      • Table 395. Interrupt Steering Register 0 - INTSTR0 (Sheet 1 of 2)
    • 10.7.14 Interrupt Steering Register 1 - INTSTR1
      • Table 396. Interrupt Steering Register 1 - INTSTR1 (Sheet 1 of 2)
    • 10.7.15 Interrupt Steering Register 2 - INTSTR2
      • Table 397. Interrupt Steering Register 2 - INTSTR2
    • 10.7.16 Interrupt Steering Register 3 - INTSTR3
      • Table 398. Interrupt Steering Register 3 - INTSTR3 (Sheet 1 of 2)
    • 10.7.17 IRQ Interrupt Source Register 0 - IINTSRC0
      • Table 399. IRQ Interrupt Source Register 0 - IINTSRC0 (Sheet 1 of 2)
    • 10.7.18 IRQ Interrupt Source Register 1 - IINTSRC1
      • Table 400. IRQ Interrupt Source Register 1 - IINTSRC1 (Sheet 1 of 2)
    • 10.7.19 IRQ Interrupt Source Register 2 - IINTSRC2
      • Table 401. IRQ Interrupt Source Register 2 - IINTSRC2
    • 10.7.20 IRQ Interrupt Source Register 3 - IINTSRC3
      • Table 402. IRQ Interrupt Source Register 3 - IINTSRC3 (Sheet 1 of 2)
    • 10.7.21 FIQ Interrupt Source Register 0 - FINTSRC0
      • Table 403. FIQ Interrupt Source Register 0 - FINTSRC0 (Sheet 1 of 2)
    • 10.7.22 FIQ Interrupt Source Register 1 - FINTSRC1
      • Table 404. FIQ Interrupt Source Register 1 - FINTSRC1 (Sheet 1 of 2)
    • 10.7.23 FIQ Interrupt Source Register 2 - FINTSRC2
      • Table 405. FIQ Interrupt Source Register 2 - FINTSRC2
    • 10.7.24 FIQ Interrupt Source Register 3 - FINTSRC3
      • Table 406. FIQ Interrupt Source Register 3 - FINTSRC3 (Sheet 1 of 2)
    • 10.7.25 Interrupt Priority Register 0 - IPR0
      • Table 407. Interrupt Priority Register 0 - IPR0
    • 10.7.26 Interrupt Priority Register 1 - IPR1
      • Table 408. Interrupt Priority Register 1 - IPR1
    • 10.7.27 Interrupt Priority Register 2 - IPR2
      • Table 409. Interrupt Priority Register 2 - IPR2
    • 10.7.28 Interrupt Priority Register 3 - IPR3
      • Table 410. Interrupt Priority Register 3 - IPR3
    • 10.7.29 Interrupt Priority Register 4 - IPR4
      • Table 411. Interrupt Priority Register 4 - IPR4
    • 10.7.30 Interrupt Priority Register 5 - IPR5
      • Table 412. Interrupt Priority Register 5 - IPR5
    • 10.7.31 Interrupt Priority Register 6 - IPR6
      • Table 413. Interrupt Priority Register 6 - IPR6
    • 10.7.32 Interrupt Priority Register 7 - IPR7
      • Table 414. Interrupt Priority Register 7 - IPR7
• 11.0 Timers
  • Figure 71. Programmable Timer Functional Diagram
  • Table 415. Timer Performance Ranges
  • 11.1 Timer Operation
    • 11.1.1 Basic Programmable Timer Operation
      • Table 416. Timer Mode Register Control Bit Summary
    • 11.1.2 Watch Dog Timer Operation
    • 11.1.3 Load/Store Access Latency for Timer Registers
      • Table 417. Timer Responses to Register Bit Settings
  • 11.2 Timer Interrupts
  • 11.3 Timer State Diagram
    • Figure 72. Timer Unit State Diagram
  • 11.4 Timer Registers
    • Table 418. Timer Registers
    • 11.4.1 Power Up/Reset Initialization
      • Table 419. Timer Power Up Mode Settings
    • 11.4.2 Timer Mode Registers - TMR0:1
      • Table 420. Timer Mode Register - TMRx
      • 11.4.2.1 Bit 0 - Terminal Count Status Bit (TMRx.tc)
      • 11.4.2.2 Bit 1 - Timer Enable (TMRx.enable)
      • 11.4.2.3 Bit 2 - Timer Auto Reload Enable (TMRx.reload)
      • 11.4.2.4 Bit 3 - Timer Register Privileged Read/Write Control (TMRx.pri)
      • 11.4.2.5 Bits 4, 5 - Timer Input Clock Select (TMRx.csel1:0)
        • Table 421. Timer Input Clock (TCLOCK) Frequency Selection
    • 11.4.3 Timer Count Register - TCR0:1
      • Table 422. Timer Count Register - TCRx
    • 11.4.4 Timer Reload Register - TRR0:1
      • Table 423. Timer Reload Register - TRRx
    • 11.4.5 Timer Interrupt Status Register - TISR
      • Table 424. Timer Interrupt Status Register - TISR
    • 11.4.6 Watch Dog Timer Control Register - WDTCR
      • Table 425. Watch Dog Timer Control Register - WDTCR
    • 11.4.7 Watch Dog Timer Setup Register - WDTSR
      • Table 426. Watch Dog Timer Setup Register - WDTSR
  • 11.5 Uncommon TCRX and TRRX Conditions
    • Table 427. Uncommon TMRx Control Bit Settings
• 12.0 SMBus Interface Unit
  • 12.1 Overview
  • 12.2 SMBus Interface
    • Table 428. SMBus Interface Pins
  • 12.3 System Management Bus Interface
    • 12.3.1 SMBus Controller
      • 12.3.1.1 SMBus Commands
        • Table 429. SMBus Command Encoding
      • 12.3.1.2 Initialization Sequence
    • 12.3.2 SMBus Signaling
      • 12.3.2.1 Overview
      • 12.3.2.2 Waveforms
        • Figure 73. Basic SMBus Transfer Waveform
        • 12.3.2.2.1 Start Phase
          • Figure 74. Start (S) / Repeat Start (Sr) Signaling
        • 12.3.2.2.2 Stop Phase
          • Figure 75. Stop (P) Signaling
        • 12.3.2.2.3 ACK/NACK
          • Figure 76. ACK (A) Signaling
          • Figure 77. NACK (N) Signaling
        • 12.3.2.2.4 Wait States
    • 12.3.3 Architecture
      • Table 430. SMBus Interface Registers for Configuration Space Access
      • Table 431. SMBus Interface Registers for Memory Space Access
      • 12.3.3.1 Data Transfer Examples
      • 12.3.3.2 Configuration and Memory Reads
        • Table 432. SMBus Status Byte Encoding
        • Figure 78. DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Enabled)
        • Figure 79. DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Enabled)
        • Figure 80. DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled)
        • Figure 81. DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled)
        • Figure 82. DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Disabled)
        • Figure 83. DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled)
        • Figure 84. DWORD Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC Enabled)
        • Figure 85. DWORD Memory Read Protocol (SMBus Word Write/Byte Read, PEC Enabled)
      • 12.3.3.3 Configuration and Memory Writes
        • Figure 86. DWORD Configuration Write Protocol (SMBus Block Write, PEC Enabled)
        • Figure 87. DWORD Memory Write Protocol (SMBus Word Write, PEC Enabled)
        • Figure 88. DWORD Configuration Write Protocol (SMBus Byte Write, PEC Enabled)
    • 12.3.4 Error Handling
    • 12.3.5 SMBus Interface Reset
  • 12.4 Register Definitions
    • Table 433. SMBus Register Summary
    • 12.4.1 SMBus Controller Command Register - SM_CMD
      • Table 434. SMBus Controller Command Register - SM_CMD
    • 12.4.2 SMBus Controller Byte Count Register - SM_BC
      • Table 435. SMBus Controller Byte Count Register - SM_BC
    • 12.4.3 SMBus Controller ADDR3 Register - SM_ADDR3
      • Table 436. SMBus Controller ADDR3 Register - SM_ADDR3
    • 12.4.4 SMBus Controller ADDR2 Register - SM_ADDR2
      • Table 437. SMBus Controller ADDR2 Register - SM_ADDR2
    • 12.4.5 SMBus Controller ADDR1 Register Number - SM_ADDR1
      • Table 438. SMBus Controller ADDR1 Register Number - SM_ADDR1
    • 12.4.6 SMBus Controller ADDR0 Register Number - SM_ADDR0
      • Table 439. SMBus Controller ADDR0 Register Number - SM_ADDR0
    • 12.4.7 SMBus Controller Data Register - SM_DATA
      • Table 440. SMBus Controller Data Register - SM_DATA
    • 12.4.8 SMBus Controller Status Register - SM_STS
      • Table 441. SMBus Controller Status Register - SM_STS
• 13.0 UARTs
  • 13.1 Overview
    • 13.1.1 Compatibility with 16550 and 16750
  • 13.2 Signal Descriptions
    • Table 442. UART Signal Descriptions
  • 13.3 Theory of Operation
    • Figure 89. Example UART Data Frame
    • Figure 90. NRZ Bit Encoding Example - (0100 1011)
    • 13.3.1 FIFO Interrupt Mode Operation
      • 13.3.1.1 Receiver Interrupt
      • 13.3.1.2 Transmit Interrupt
    • 13.3.2 Removing Trailing Bytes In Interrupt Mode
      • 13.3.2.1 Character Time-out Interrupt
    • 13.3.3 FIFO Polled Mode Operation
      • 13.3.3.1 Receive Data Service
      • 13.3.3.2 Transmit Data Service
    • 13.3.4 Autoflow Control
      • 13.3.4.1 RTS Autoflow
      • 13.3.4.2 CTS Autoflow
    • 13.3.5 Auto-Baud-Rate Detection
      • Equation 17. Baud Rate Formula
      • Table 443. Divisor Values for Typical Baud Rates
    • 13.3.6 Manual Baud Rate Selection
  • 13.4 Register Descriptions
    • Table 444. UART Register Addresses as Offsets of a Base
    • Table 445. UART Unit Registers
    • Table 446. UART Register MMR Addresses
    • 13.4.1 UART x Receive Buffer Register
      • Table 447. UART x Receive Buffer Register - (UxRBR)
    • 13.4.2 UART x Transmit Holding Register
      • Table 448. UART x Transmit Holding Register - (UxTHR)
    • 13.4.3 UART x Interrupt Enable Register
      • Table 449. UART x Interrupt Enable Register - (UxIER)
    • 13.4.4 UART x Interrupt Identification Register
      • Table 450. UART x Interrupt Identification Register - (UxIIR)
      • Table 451. Interrupt Identification Register Decode
    • 13.4.5 UART x FIFO Control Register
      • Table 452. UART x FIFO Control Register - (UxFCR) (Sheet 1 of 2)
    • 13.4.6 UART x Line Control Register
      • Table 453. UART x Line Control Register - (UxLCR) (Sheet 1 of 2)
    • 13.4.7 UART x Modem Control Register
      • Table 454. UART x Modem Control Register - (UxMCR) (Sheet 1 of 2)
    • 13.4.8 UART x Line Status Register
      • Table 455. UART x Line Status Register - (UxLSR) (Sheet 1 of 3)
      • Table 456. UART x Modem Status Register
      • Table 457. UART x Modem Status Register - (UxMSR)
    • 13.4.9 UART x Scratchpad Register
      • Table 458. UART x Scratchpad Register - (UxSCR)
    • 13.4.10 Divisor Latch Registers
      • Table 459. UART x Divisor Latch Low Register - (UxDLL)
      • Table 460. UART x Divisor Latch High Register - (UxDLH)
    • 13.4.11 UART x FIFO Occupancy Register
      • Table 461. UART x FIFO Occupancy Register - (UxFOR)
    • 13.4.12 UART x Auto-Baud Control Register
      • Table 462. UART x Auto-Baud Control Register - (UxABR)
    • 13.4.13 UART x Auto-Baud Count Register
      • Table 463. UART x Auto-Baud Count Register - (UxACR)
• 14.0 I2C Bus Interface Units
  • 14.1 Overview
  • 14.2 Theory of Operation
    • Table 464. I2C Bus Definitions
    • Figure 91. I2C Bus Configuration Example
    • 14.2.1 Operational Blocks
      • Figure 92. I2C Bus Interface Unit Block Diagram
    • 14.2.2 I2C Bus Interface Modes
      • Table 465. Modes of Operation
    • 14.2.3 Start and Stop Bus States
      • Table 466. START and STOP Bit Definitions
      • Figure 93. Start and Stop Conditions
      • 14.2.3.1 START Condition
      • 14.2.3.2 No START or STOP Condition
      • 14.2.3.3 STOP Condition
        • Figure 94. START and STOP Conditions
  • 14.3 I2C Bus Operation
    • Equation 18. SCL Transition Period
    • 14.3.1 Data and Addressing Management
      • 14.3.1.1 Addressing a Slave Device
        • Figure 95. Data Format of First Byte in Master Transaction
    • 14.3.2 I2C Acknowledge
      • Figure 96. Acknowledge on the I2C Bus
    • 14.3.3 Arbitration
      • 14.3.3.1 SCL Arbitration
        • Figure 97. Clock Synchronization During the Arbitration Procedure
      • 14.3.3.2 SDA Arbitration
        • Figure 98. Arbitration Procedure of Two Masters
    • 14.3.4 Master Operations
      • Table 467. Master Transactions (Sheet 1 of 2)
      • Figure 99. Master-Receiver Read from Slave-Transmitter
      • Figure 100. Master-Receiver Read from Slave-Transmitter / Repeated Start /Master-Transmitter Write to Slave-Receiver
      • Figure 101. A Complete Data Transfer
    • 14.3.5 Slave Operations
      • Table 468. Slave Transactions
      • Figure 102. Master-Transmitter Write to Slave-Receiver
      • Figure 103. Master-Receiver Read to Slave-Transmitter
      • Figure 104. Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter Write to Slave-Receiver
    • 14.3.6 General Call Address
      • Figure 105. General Call Address
      • Table 469. General Call Address Second Byte Definitions
  • 14.4 Slave Mode Programming Examples
    • 14.4.1 Initialize Unit
    • 14.4.2 Write 1 Byte as a Slave
    • 14.4.3 Read 2 Bytes as a Slave
  • 14.5 Master Programming Examples
    • 14.5.1 Initialize Unit
    • 14.5.2 Write 1 Byte as a Master
    • 14.5.3 Read 1 Byte as a Master
    • 14.5.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master
    • 14.5.5 Read 2 Bytes as a Master - Send STOP Using the Abort
  • 14.6 Glitch Suppression Logic
  • 14.7 Reset Conditions
  • 14.8 Register Definitions
    • Table 470. I2C Register Summary
    • 14.8.1 I2C Control Register x - ICRx
      • Table 471. I2C Control Register x - ICRx (Sheet 1 of 2)
    • 14.8.2 I2C Status Register x - ISRx
      • Table 472. I2C Status Register x - ISRx (Sheet 1 of 2)
    • 14.8.3 I2C Slave Address Register x - ISARx
      • Table 473. I2C Slave Address Register x - ISARx
    • 14.8.4 I2C Data Buffer Register x - IDBRx
      • Table 474. I2C Data Buffer Register x - IDBRx
    • 14.8.5 I2C Bus Monitor Register x - IBMRx
      • Table 475. I2C Bus Monitor Register x - IBMRx
    • 14.8.6 I2C Manual Bus Control Register x - IMBCRx
      • Table 476. I2C Manual Bus Control Register x - IMBCRx
• 15.0 General Purpose I/O Unit
  • 15.1 General Purpose Input Output Support
    • 15.1.1 General Purpose Inputs
    • 15.1.2 General Purpose Outputs
    • 15.1.3 Reset Initialization of General Purpose I/O Function
  • 15.2 Register Definitions
    • Table 477. General Purpose I/O Registers Addresses
    • 15.2.1 GPIO Output Enable Register - GPOE
      • Table 478. GPIO Output Enable Register - GPOE
    • 15.2.2 GPIO Input Data Register - GPID
      • Table 479. GPIO Input Data Register - GPID (Sheet 1 of 2)
    • 15.2.3 GPIO Output Data Register - GPOD
      • Table 480. GPIO Output Data Register - GPOD
• 16.0 PMON Unit
  • 16.1 PMON Counters
  • 16.2 Overview
    • Figure 106. Example Block Diagram of Component with Counter
    • 16.2.1 Clock Counter Control
      • Figure 107. Conceptual Diagram of Counter Array
  • 16.3 Definitions
    • Figure 108. Example Block Diagram of Single PMON Counter
  • 16.4 Data Collection
    • 16.4.1 Time Based Sampling
      • Figure 109. Flowchart of Example Commands Sequence
      • Table 481. Simple Time Based Counting of Events Example
      • Figure 110. Block Diagram and Waveforms of Time Based Sampling Example
    • 16.4.2 Hardware Event Based Control
      • Table 482. Hardware Event Based Event Counting Example
      • Figure 111. Block Diagram and Waveforms of Time Based Sampling Example
    • 16.4.3 Incrementing By More Than 1
      • Figure 112. Block Diagram & Waveforms of Time Based Sampling Example
    • 16.4.4 Queue Analysis
      • Table 483. Hardware Event Based Event Counting Example
      • Figure 113. Block Diagram & Waveforms of Time Based Sampling Example
      • Table 484. Queue Depth Histogram Example
      • Table 485. Head of Queue Histogram Example
      • Figure 114. Block Diagram of HOQ Histogram Example
      • Figure 115. Waveforms of HOQ Histogram Example
      • Figure 116. Processing of HOQ Histogram Example
      • Figure 117. Output from HOQ Histogram Example
  • 16.5 Non-Register-Based Interfaces
    • 16.5.1 Events Input Port
    • 16.5.2 Output Signals
      • 16.5.2.1 Indicator Output
        • Figure 118. Indicator Tree
      • 16.5.2.2 Interrupt Output
    • 16.5.3 Internal Bus Addresses
      • Table 486. PMON Internal Bus Memory Mapped Register Range Offsets
      • Table 487. PMON Register Summaries
    • 16.5.4 PMON Feature Enable Register - PMONEN
      • Table 488. PMON Feature Enable Register - PMONEN
    • 16.5.5 PMON Status Register - PMONSTAT
      • Table 489. PMON Status Register - PMONSTAT
    • 16.5.6 PMON Memory Mapped Registers
      • Table 490. PMON Internal Bus Memory Mapped Register Range Offsets
      • Table 491. PMON Register Summaries
      • 16.5.6.1 PMON Command Register 0-7 - PMON_CMD[0:7]
        • Table 492. PMON Command Register 0-7 - PMON_CMD[0:7] (Sheet 1 of 4)
      • 16.5.6.2 PMON Event Register 0-7 - PMON_EVR[0:7]
        • Table 493. PMON Event Register 0-7 - PMON_EVR[0:7]
      • 16.5.6.3 PMON Status Register 0-7 - PMON_STS[0:7]
        • Table 494. PMON Status Register 0-7 - PMON_STS[0:7] (Sheet 1 of 2)
      • 16.5.6.4 PMON Data Register 0-7 - PMON_DATA[0:7]
        • Table 495. PMON DATA Register 7-0 - PMON_DATA[7:0]
    • 16.5.7 PMON Events
      • Table 496. Event Selection Code Summary
      • 16.5.7.1 Null Event
        • Table 497. Intel® 413808 and 413812 I/O Controllers in TPER Mode PMON Clock Events
      • 16.5.7.2 Clock Events
        • Table 498. Intel® 413808 and 413812 I/O Controllers PMON Clock Events
      • 16.5.7.3 Threshold Events
        • Table 499. Intel® 413808 and 413812 I/O Controllers PMON Threshold Events
      • 16.5.7.4 PCI Interface Events
        • Table 500. PCI Interface Events
      • 16.5.7.5 PCI Express Interface Events
        • Table 501. PCI Express Interface Summary
      • 16.5.7.6 North Internal Bus Events
        • Table 502. North Internal Bus Source Select Summary
        • Table 503. North Internal Bus Initiator Events
      • 16.5.7.7 South Internal Bus Events
        • Table 504. South Internal Bus Source Select Summary
        • Table 505. South Internal Bus Initiator Events
• 17.0 Clocking and Reset
  • 17.1 Clocking Overview
    • Figure 119. Intel® 413808 and 413812 I/O Controllers in TPER Mode Clocking Regions Diagram
    • 17.1.1 Clocking Theory of Operation
      • 17.1.1.1 Clocking Region 1 (PCI Express)
      • 17.1.1.2 Clocking Region 2 (PCI)
        • 17.1.1.2.1 Central Resource Mode (PCIX_EP# = ‘1’)
          • Table 506. PCI Bus Frequency Initialization
          • Table 507. CR_FREQ[1:0] Encoding
        • 17.1.1.2.2 cPCI Hot-Swap Mode (PCIX_EP# = ‘0’ and HS_SM# = ‘0’)
          • Table 508. HS_FREQ Encoding
        • 17.1.1.2.3 End Point Mode (PCIX_EP# = 0 and HS_SM# = 1)
          • Table 509. PCI-X Initialization Pattern1
        • 17.1.1.2.4 Secondary Clock Outputs
          • Table 510. Secondary Clock Output Control
      • 17.1.1.3 Clocking Region 3 (Internal Bus)
      • 17.1.1.4 Clocking Region 4 (Peripheral Bus Interface)
      • 17.1.1.5 Clocking Region 5
      • 17.1.1.6 Clocking Region 7 (Intel XScale® Processor)
    • 17.1.2 Clocking Region Summary
      • Table 511. Clock Pin Summary
  • 17.2 Reset Overview
    • 17.2.1 Fundamental Reset
    • 17.2.2 Software Reset
    • 17.2.3 Secondary Bus Reset
    • 17.2.4 PCI Reset
    • 17.2.5 PCI Express Hot Reset
    • 17.2.6 WARM_RST# Reset Mechanism
    • 17.2.7 Intel XScale® Processor Reset Mechanism
      • Table 512. Core Reset Control Bit Locations
    • 17.2.8 Internal Bus Reset
      • Table 513. Internal Bus Reset Control Bit Locations
      • Table 514. Internal Bus Reset Summary (Sheet 1 of 2)
  • 17.3 Reset Pins
    • Table 515. Reset Pin Summary
  • 17.4 Device Function Select
    • Table 516. TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=1)
    • Table 517. Non-TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=0)
  • 17.5 Reset Strapping Options
    • Table 518. Reset Strap Signals (Sheet 1 of 2)
• 18.0 Test Logic Unit and Testability
  • 18.1 Overview
  • 18.2 IEEE 1149.1 Standard Test Access Port (TAP)
    • Figure 120. IEEE 1149.1 Std. Block Diagram
    • 18.2.1 TAP Pin Description
      • 18.2.1.1 Test Clock (TCK)
      • 18.2.1.2 Test Mode Select (TMS)
      • 18.2.1.3 Test Data Input (TDI)
      • 18.2.1.4 Test Data Output (TDO)
      • 18.2.1.5 Asynchronous Reset (TRST#)
    • 18.2.2 TAP Controller
      • Figure 121. Timing of Actions in a TAP Controller State
      • Figure 122. TAP Controller State Diagram
      • 18.2.2.1 Test-Logic-Reset State
      • 18.2.2.2 Run-Test/Idle State
      • 18.2.2.3 Select-DR-Scan State
      • 18.2.2.4 Capture-DR State
      • 18.2.2.5 Shift-DR State
      • 18.2.2.6 Exit1-DR State
      • 18.2.2.7 Pause-DR State
      • 18.2.2.8 Exit2-DR State
      • 18.2.2.9 Update-DR State
      • 18.2.2.10 Select-IR-Scan State
      • 18.2.2.11 Capture-IR State
      • 18.2.2.12 Shift-IR State
      • 18.2.2.13 Exit1-IR State
      • 18.2.2.14 Pause-IR State
      • 18.2.2.15 Exit2-IR State
      • 18.2.2.16 Update-IR State
    • 18.2.3 TAP Controller Registers
      • 18.2.3.1 Instruction Register
      • 18.2.3.2 Instructions
        • Table 519. TLU TAP Controller Instruction Set
      • 18.2.3.3 Boundary-Scan Register
      • 18.2.3.4 Bypass Register
      • 18.2.3.5 Device Identification Register
        • Figure 123. IOP Device ID Register
        • Table 520. IOP Device ID Register Field Definitions
        • Table 521. IOP Device ID Register Settings
  • 18.3 Definition of Terms
• 19.0 Peripheral Registers
  • 19.1 Overview
  • 19.2 Accessing Peripheral Memory-Mapped Registers
  • 19.3 Accessing Peripheral Registers Using the Core Coprocessor Register Interface
  • 19.4 Architecturally Reserved Memory Space
  • 19.5 Default Memory Space Setup
    • Figure 124. Intel® 413808 and 413812 I/O Controllers in TPER Mode Memory Address Space
  • 19.6 Peripheral Memory-Mapped Register Address Space
    • Table 522. PMMR Base Address Register (PMMRBAR) Default Value
    • Table 523. Local Addresses for Integrated Peripherals (Sheet 1 of 3)
    • 19.6.1 Internal Units
      • 19.6.1.1 Peripheral Bus Interface Unit
        • Table 524. PBI Base Address Offset.
        • Table 525. Peripheral Bus Interface Unit
      • 19.6.1.2 System Controller
        • Table 526. SC Base Address Offset.
        • Table 527. System Controller Unit
      • 19.6.1.3 Internal Bus Bridge
        • Table 528. Internal Bus Bridge Base Address Offset.
        • Table 529. Internal Bus Bridge
      • 19.6.1.4 I/O Pad Control
        • Table 530. I/O Pad Control Base Address Offset.
        • Table 531. I/O Pad Control Unit
      • 19.6.1.5 UART 0-1
        • Table 532. UART 0-1 Offset.
        • Table 533. UART
      • 19.6.1.6 GPIO
        • Table 534. GPIO Offset.
        • Table 535. GPIO
      • 19.6.1.7 I2C Bus Interface Unit 0-2
        • Table 536. I2C 0-2 Offset.
        • Table 537. I2C Unit
      • 19.6.1.8 Messaging Unit
        • Table 538. Messaging Unit Offset.
        • Table 539. Messaging Unit (Sheet 1 of 2)
      • 19.6.1.9 PMON Unit
        • Table 540. PMON Unit Base Address Offset.
        • Table 541. PMON Unit
    • 19.6.2 Host Interface Units
      • Table 542. PCI Function MMR Locations
      • 19.6.2.1 Address Translation Unit (PCI-X)
        • Table 543. Intel® 413808 and 413812 I/O Controllers ATUX Configuration Space Base Address Offset
        • Table 544. Address Translation Unit Registers - ATUX (Sheet 1 of 3)
      • 19.6.2.2 Address Translation Unit (PCI-E)
        • Table 545. Intel® 413808 and 413812 I/O Controllers ATUE Configuration Space Base Address Offset
        • Table 546. Address Translation Unit Registers - ATUE (Sheet 1 of 4)
  • 19.7 PCI Configuration Space
    • Table 547. Intel® 413808 and 413812 I/O Controllers in TPER Mode PCI Function Visibility
  • 19.8 Coprocessor Register Space
    • Table 548. Coprocessor Registers Assigned to Integrated Peripherals
    • Table 549. Coprocessor Register Locations (Sheet 1 of 4)